mc13109 Freescale Semiconductor, Inc, mc13109 Datasheet - Page 17

• Manufacturer Part Number: mc13109
• Description: Universal Cordless Telephone Subsystem
• Manufacturer: Freescale Semiconductor, Inc

register determines whether the data is latched into the
address register or a data register. Figure 12 shows the
address and data programming diagrams. In the data
programming mode, there must not be any clock transitions
when “EN” is high. The clock can be in a high state (default
high) or a low state (default low) but must not have any
transitions during the “EN” high state. The convention in
these figures is that latch bits to the left are loaded into the
shift register first.
after the power supply has reached its minimum level during
power–up (See Figure 13). The MPU Interface shift registers
and data latches are operational in all four power saving
modes; Inactive, Standby, R x , and Active Modes. Data can
be loaded into the shift registers and latched into the latch
registers in any of the operating modes.
Data
Data
MOTOROLA ANALOG IC DEVICE DATA
The state of the EN pin when clocking data into the shift
The MPU serial interface is fully operational within 100 s
EN
EN
Figure 12. Microprocessor Interface Programming
MSB
MSB
Address Register Programming Mode
Data Register Programming Mode
Mode Diagrams
8–Bit Address
16–Bit Data
LSB
LSB
Latch
Latch
MC13109
Status Out
registers have been reset to their power–up default values.
Latch power–up default values are given in Figure 32. If there
is a power glitch or ESD event which causes the latch
registers to be reset to their default values, the “Status Out”
pin will indicate this to the MPU so it can reload the correct
information into the latch registers.
Data Registers
which are used to select each of these registers. Latch bits to
the left (MSB) are loaded into the shift register first. The LSB
bit must always be the last bit loaded into the shift register.
“Don’t care” bits can be loaded into the shift register first if
8–bit bytes of data are loaded.
Latch bits not at power–up default value
Latch bits at power–up default value
This is a digital output which indicates whether the latch
Figure 15 shows the data latch registers and addresses
Clk, EN
Data,
V CC
Figure 13. Microprocessor Serial Interface
Status Latch Register Bits
Figure 14. Status Out Operation
Power–Up Delay
2.0 V
t puMPU
Logic Level
Status Out
0
1
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