aduc7023bcpz62irl Analog Devices, Inc., aduc7023bcpz62irl Datasheet - Page 43
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aduc7023bcpz62irl
Manufacturer Part Number
aduc7023bcpz62irl
Description
Precision Analog Microcontroller, 12-bit Analog I/o, Arm7tdmi Mcu With Enhanced Irq Handler
Manufacturer
Analog Devices, Inc.
Datasheet
1.ADUC7023BCPZ62IRL.pdf
(96 pages)
OTHER ANALOG PERIPHERALS
DAC
The ADuC7023 incorporates four, 12-bit voltage output DACs
on chip. Each DAC has a rail-to-rail voltage output buffer
capable of driving 5 kΩ/100 pF.
Each DAC has two selectable ranges: 0 V to V
gap 2.5 V reference) and 0 V to AV
The signal range is 0 V to AV
By setting RSTCFG Bit 2, the DAC output pins can retain their
state during a watchdog or software reset.
MMRs Interface
Each DAC is independently configurable through a control
register and a data register. These two registers are identical for
the four DACs. Only DAC0CON (see Table 37) and DAC0DAT
(see Table 38) are described in detail in this section.
DACxCON Registers
Name
DAC0CON
DAC1CON
DAC2CON
DAC3CON
Table 37. DAC0CON MMR Bit Designations
Bit
7
6
5
4
3
2
1 to 0
Value
00
01
10
11
Address
0xFFFF0600
0xFFFF0608
0xFFFF0610
0xFFFF0618
Name
DACBY
DACCLK
DACCLR
Description
Reserved.
This bit is set to bypass the DAC
output buffer.
This bit is cleared to enable the
DAC output buffer.
DAC update rate.
This bit is set by the user to update
the DAC using Timer1.
This bit is cleared by the user to
update the DAC using HCLK (core
clock).
DAC clear bit.
This bit is set by the user to enable
normal DAC operation.
This bit is cleared by the user to
reset data register of the DAC to 0.
Reserved. This bit remains at 0.
Reserved. This bit remains at 0.
DAC range bits.
Power-down mode. The DAC
output is in tristate.
Reserved.
0 V to V
0 V to AV
DD
.
Default Value
0x00
0x00
0x00
0x00
DD
REF
.
DD
(2.5 V) range.
range.
REF
(internal band
Access
R/W
R/W
R/W
R/W
Rev. 0 | Page 43 of 96
DACxDAT Registers
Name
DAC0DAT
DAC1DAT
DAC2DAT
DAC3DAT
Table 38. DAC0DAT MMR Bit Designations
Bit
31 to 28
27 to 16
15 to 0
Using the DACs
The on-chip DAC architecture consists of a resistor string DAC
followed by an output buffer amplifier. The functional equivalent
is shown in Figure 32.
As illustrated in Figure 32, the reference source for each DAC
is user-selectable in software. It can be either AV
0-to-AV
0 V to the voltage at the AV
output transfer function spans from 0 V to the internal 2.5 V
reference, V
The DAC output buffer amplifier features a true, rail-to-rail
output stage implementation. This means that when unloaded,
each output is capable of swinging to within less than 5 mV of
both AV
(when driving a 5 kΩ resistive load to ground) is guaranteed
through the full transfer function except Code 0 to Code 100,
and, in 0-to-AV
Linearity degradation near ground and V
ration of the output amplifier, and a general representation of its
effects (neglecting offset and gain error) is illustrated in Figure 33.
The dotted line in Figure 33 indicates the ideal transfer function,
and the solid line represents what the transfer function may
look like with endpoint nonlinearities due to saturation of the
DD
DD
mode, the DAC output transfer function spans from
and ground. Moreover, the DAC linearity specification
DAC
REF
AV
V
.
REF
REF
Address
0xFFFF0604
0xFFFF060C
0xFFFF0614
0xFFFF061C
DD
DD
Description
Reserved.
Reserved.
12-bit data for DAC0.
mode only, Code 3995 to Code 4095.
Figure 32. DAC Structure
R
R
R
R
R
DD
pin. In 0-to-V
Default Value
0x00000000
0x00000000
0x00000000
0x00000000
DD
REF
is caused by satu-
mode, the DAC
DD
ADuC7023
DAC0
or V
REF
Access
R/W
R/W
R/W
R/W
. In