lm2507gr National Semiconductor Corporation, lm2507gr Datasheet - Page 13

• Manufacturer Part Number: lm2507gr
• Description: Low Power Mobile Pixel Link Mpl Level 0, 16-bit Cpu Display Interface Serializer And Deserializer
• Manufacturer: National Semiconductor Corporation

Functional Description
SLAVE OUTPUT TIMING
The Slave output recreates the transaction that was sent to
the Master. However exact timing of the Slave output is not
identical to the Master input. The active pulse (WR
output pulse) is a function of the MC cycle rate alone. The
width applied on the Master input (assuming it meets set and
hold requirements), is not regenerated by the Slave output.
Also with WRITE transactions the output state is held until
the next transaction requires them to be updated. For ex-
ample after a i80 WRITE to CS1*, the A/D, DATAn, and CS1*
output will remain static and hold their last state. CS1* will
remain Low until a transaction to CS2* or a PowerDown
event. This is acceptable to the target device as normally
both an active CS and RD or WR signal is required.
T10
T12
T13
T14
T15
T16
T17
No.
T11
T1
T2
T3
T4
T5
T6
T7
T8
T9
MasterOUT
MasterOUT
MasterOUT
MasterOUT
MasterOUT
MasterIN
MasterIN
Master
Master
Master
Slave
Slave
Slave
Slave
Slave
Slave
Slave
Set Up Time (A/D, RD*) and Data On Time
Hold Time (A/D, RD*) and Data Off Time
Master Latency
Slave Latency
Read* Delay
Read Low Pulse Width
Data Set Up Time
Data Hold Time
Slave Read Latency
MST Read Latency and INTR Delay
Data Delay
Data Valid after Strobe
RD* active pulse width
INTR De-assert
Recovery Time, (Note 9)
INTR Response
IDR Delay, IDR = High, Figure 13
TABLE 3. READ — i80 CPU Interface Parameters
FIGURE 13. Slave Output Timing with IDR = H
(Continued)
Parameter
*
and RD
*
13
On the display side, the Slave can be configured through the
IDR input to issue one or two read transactions to the
peripheral. If configured for two read transactions, it will take
longer for the INTR signal to be asserted from the Master to
account for the time taken for the remote dummy read. Use
of this mode allows for consistent behavior from the periph-
eral regardless of the use of the MPL link (LM2507) or not.
See Figure 13.
Compatibility of target device’s timing requirements should
be checked. Check that the active pulse is wide enough for
the current settings. If the SLV output is too fast, a slower MC
rate should be chosen (use a lower input CLK frequency).
Min
3.5
2.5
5
5
1
0
>
Typ
7.5
14
13
7
4
1
6
4
5
5
4
50
20186034
Max
41
www.national.com
MC Cycles
MC Cycles
MC Cycles
MC Cycles
MC Cycles
MC Cycles
MC Cycles
MC Cycles
MC Cycles
Units
ns
ns
ns
ns
ns
ns
ns
ns