lm2507gr National Semiconductor Corporation, lm2507gr Datasheet - Page 6

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lm2507gr

Manufacturer Part Number
lm2507gr
Description
Low Power Mobile Pixel Link Mpl Level 0, 16-bit Cpu Display Interface Serializer And Deserializer
Manufacturer
National Semiconductor Corporation
Datasheet
www.national.com
Recommended Input Timing Requirements
Note 5: Total Supply Current Conditions: CPU Mode, worse case data pattern, 19.2MHz CLK, DES C
= 3.0V and V
Note 6: Applies to WR
Note 7: Maximum transition time is a function of clock rate and should be less than 30% of the clock period to preserve signal quality.
Note 8: Guaranteed functionally by the I
Note 9: This is a functional parameter and is guaranteed by design or characterization.
Timing Diagrams
Functional Description
BUS OVERVIEW
The LM2507 is a dual link MST/SLV configurable part that
supports a 8, 9 or 16-bit CPU (i80 style) interface. The MPL
physical layer is purpose-built for an extremely low power
and low EMI data transmission while requiring the fewest
number of signal lines. No external line components are
required, as termination is provided internal to the MPL
receiver. A maximum raw throughput of 320 Mbps (raw) is
possible with this chipset. When the protocol overhead is
taken into account, a maximum data throughput of 240 Mbps
is possible. The MPL interface is designed for use with
common 50Ω to 100Ω lines using standard materials and
connectors. Lines may be microstrip or stripline construction.
Total length of the interconnect is expected to be less than
20cm.
DDA
= V
DDcore
*
and RD
= 2.0V.
*
outputs only..
FIGURE 1. Serial Data Valid — SLV Input Set and Hold Time
DDZ
parameter. See also Figure 7.
FIGURE 2. SLV Output Rise and Fall Time
6
SERIAL BUS TIMING
Data valid is relative to both edges for a CPU WRITE as
shown in Figure 4 . Data valid is specified as: Data Valid
before Clock, Data Valid after Clock, and Skew between
data lines should be less than 500ps.
(Continued)
L
FIGURE 3. MPL Point-to-Point Bus
= 15pF, TYP – V
20186018
DDIO
20186016
= V
DDA
= V
DDcore
= 1.8V, MAX – V
20186002
DDIO

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