lm2507gr National Semiconductor Corporation, lm2507gr Datasheet - Page 18

• Manufacturer Part Number: lm2507gr
• Description: Low Power Mobile Pixel Link Mpl Level 0, 16-bit Cpu Display Interface Serializer And Deserializer
• Manufacturer: National Semiconductor Corporation

www.national.com
Application Information
DISPLAY APPLICATION
The LM2507 chipset is intended for interfacing between a
host (processor) and a Display. It supports a 16, 9 or 8-bit i80
CPU style interfaces and can be configured as shown in
Figure 19 . The Display side parallel bus may be connected
to one or two displays. Each display has its own chipselect
signal. The multidrop bus should be laid out to minimize any
resulting stub lengths.
FIGURE 18. MPL Interface Layout – microArray to LLP Package
FIGURE 19. CPU Mode Display Interface Application
(Continued)
18
If only one display is required, the unused CS
must be tied off (High, disabled). The unused CS
output should be left as a no-connect (NC).
If a 8-bit or 9-bit CPU bus width is desired, the unused
master inputs must be tied off (connect to Ground). The
unused Slave outputs should be left as no-connects.
*
20186001
master input
20186062
*
slave