ia3222 integration, ia3222 Datasheet
ia3222
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ia3222 Summary of contents
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... IA3222/IA3223 EZ DAA™ Chipset with Analog Interface DESCRIPTION The IA3222 and IA3223 integrated V.92 (56K) capable Data Access Arrangement (DAA) chipset is suitable for worldwide telephone line interface requirements and standards. The patented IsoBridge eliminates the need for usual telecom isolation components, such as transformers or optocouplers ...
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... DTMF Dialing ...............................................................................................................................................................................6 Pulse Dialing ................................................................................................................................................................................6 Caller ID .......................................................................................................................................................................................6 Power-Down Mode.......................................................................................................................................................................6 PACKAGE PIN DEFINITIONS.....................................................................................................................................................7 IA3223 System Side (QSOP-16) ..................................................................................................................................................7 IA3223A System Side (QSOP-20) ...............................................................................................................................................8 IA3222A Line Side (SOIC-8) ........................................................................................................................................................9 IA3222B Line Side (MSOP-10) ....................................................................................................................................................9 ELECTRICAL SPECIFICATIONS..............................................................................................................................................10 Absolute Maximum Ratings........................................................................................................................................................10 Recommended Operating Conditions ........................................................................................................................................10 DC Characteristics .....................................................................................................................................................................11 AC Characteristics......................................................................................................................................................................11 Off-Hook Receiver Performance ................................................................................................................................................12 On-Hook Receiver (Caller ID) Performance at 48V Transmitter Performance ...
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... SURGES, ISOLATION AND EMC .............................................................................................................................................35 Safety Isolation and Differential Surges .....................................................................................................................................35 Power-Line Cross.......................................................................................................................................................................37 Common-Mode Noise from the Mains Supply............................................................................................................................38 EMC ...........................................................................................................................................................................................39 RF Susceptibility ........................................................................................................................................................................39 RETURN LOSS AND TRANS-HYBRID RETURN LOSS ..........................................................................................................40 PACKAGE INFORMATION .......................................................................................................................................................42 QSOP-16 and QSOP-20 Packages............................................................................................................................................42 MSOP-10 Package.....................................................................................................................................................................42 SOIC-8 Package (JEDEC Outline MS-012AA)...........................................................................................................................42 ORDERING INFORMATION......................................................................................................................................................43 IA3222/IA3223 3 ...
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... Figure 22: Transmit gain versus ACIN capacitor................................................................................................................................... 18 Figure 23: Application schematic .......................................................................................................................................................... 22 Figure 24: Application schematic for legacy TBR21 current-limit support .......................................................................................... 24 Figure 25: IA3222/3223 evaluation board .......................................................................................................................................... 26 Figure 26: IA3222/3223 evaluation board layout ............................................................................................................................... 27 Figure 27: Single-ended interface ......................................................................................................................................................... 29 Figure 28: Differential interface — without reference .......................................................................................................................... 29 Figure 29: Differential interface — with reference................................................................................................................................ 29 ...
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... IA3222 senses an excessive loop current (about 170mA) when off hook, it will immediately go on hook. This will result in oscillation since in this case the IA3222 still sees an off-hook command and therefore keeps trying to go back off hook. While a fault condition exists, the LD status bit is high. ...
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... The IA3222 meets pulse-dialing overshoot requirements on inductive lines for Australia and a few other countries. Caller ID When the device is on hook, the Caller ID audio signal is available at the receiver output pin of the IA3223 ...
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... Optional external clock; this pin may be left open. AIO External capacitor #2 connection AIO External capacitor #1 connection AI DAA optional DC offset; this pin may be left open. AIO Line-Side IsoBridge interface reference ground S Positive power supply AI Line-Side IsoBridge interface for receiver path S System ground AO Line-Side IsoBridge interface for transmitter path IA3222/IA3223 7 ...
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... Off hook, active high, ORed with internal OFH control bit AIO External capacitor #2 connection AIO External capacitor #1 connection AI DAA optional DC offset; this pin may be left open. AIO Line-Side IsoBridge interface reference ground S Positive power supply AI Line-Side IsoBridge interface for receiver path S System ground AO Line-Side IsoBridge interface for transmitter path IA3222/IA3223 8 ...
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... IA3222A Line Side Pin Definitions Pin Number Pin Name Pin Function 1 Hook Hook-switch control 2 ICT Line-Side IsoBridge 3 ICR Line-Side IsoBridge 4 ICG Line-Side IsoBridge 5 HCap Holding capacitor connection 6 Receiver path sensing capacitor input GND Device ground 8 Device supply, self regulated through hook-switch transistor ...
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... Data in to clock rising edge setup time tdih Data in to clock rising edge hold time IA3222 power derating over 25 ºC ambient Note: The AC pin may be left open, in which case this internal bias voltage needs to be decoupled to the audio ground by REF means of a 100nF capacitor ...
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... Data (read) Data out Data out Min. -10 0 Min. 67.2 tcdo tcdo Floating DO3 DO2 Figure 2: Serial interface read-cycle timing diagram IA3222/IA3223 Typ. Max. Unit 10 µA 240 mV 0 RMS 25 V RMS 30 V RMS 40 V RMS 1.50 1. kΩ ...
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... V , high gain setting PP DD 1kHz, 100 low gain setting PP DD 120Hz IA3222/IA3223 Min. Typ. Max. Unit -85 dBm - dBm ...
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... DC coupled f > 3400Hz, DC coupled 1kHz, 100 high headroom PP DD 1kHz, 100 other headrooms > 3400Hz, DC coupled, high headroom f > 3400Hz, DC coupled, other headrooms f = 1000Hz 3000Hz IA3222/IA3223 Min. Typ. Max. Unit -82 dBm - 0.5 ±dB 0.5 ± ...
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... 20mA, no current limit, high headroom 42mA, TBR21 current limit, normal headroom 50mA, TBR21 current limit, normal headroom DD TBR21 legacy mode 230 Ω feed IA3222/IA3223 Min. Typ. Max. Unit 2.47 V 130 170 210 mA 80 ...
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... IA3222/IA3223 500 1000 1500 2000 2500 3000 Aus tralia, LP[5:4]=01 New Zealand, LP[5:4]=01 TBR21, LP[5:4]=01 Figure 4: Transmit gain with complex loads Receive gain versus frequency (Hz) 500 1000 1500 2000 2500 3000 600 Ω, LP[5:4]=00 600 Ω, LP[5:4]=01 Aus tralia, LP[5:4]=01 New Zealand, LP[5:4]=01 Figure 6: Receive gain versus frequency ...
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... Figure 14: Return loss for complex modes IA3222/IA3223 Snoop noise (dBV) versus DC voltage ( Low gain High gain Voltage vs. current, TBR21 current limit Voltage vs. current, TBR21 current limit Loop current (mA) ...
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... Hi hdrm, TH=3 Lo hdrm, TH=3 Figure 20: Transmitter-path PSR aliasing into audio band with IA3222/IA3223 1000 1500 2000 2500 3000 Aus tralia, LP[5:4]=01 New Zealand, LP[5:4]=01 TBR21, LP[5:4]=01 Current-sensor gain versus temperature - Temperature (°C) ...
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... Figure 22: Transmit gain versus ACIN capacitor IA3222/IA3223 Out-of-band frequencies aliased into the transmitter and receiver paths 100 1000 10000 Frequency (kHz) Tx out-of-band rejection Hybrid out-of-band rejection Receiver out-of-band spurs Receiver out-of-band spurs ...
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... Device powered down (Note) (Note) Cx required? IA3222A IA3222B (IA3222B only) Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes IA3222/IA3223 D0 PWD LP2 REVID RTH0 LP F0 Reserved Reset state Low High Low Low Cx1 required? (IA3222B only) Yes Yes Yes 19 ...
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... Voltage below ring threshold No loop-current drop Voltage above LIU threshold Line active No change in line-in-use status No parallel-pickup event Line reversed IA3222/IA3223 Status When Bit is High Voltage above ring threshold Loop-current drop Voltage below LIU threshold Line disconnected or line fault Change in line-in-use status ...
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... Table represents clock frequencies typically used for PCM interface devices external clock can be used to synchronize an external codec with the DAA in order to avoid aliasing. Minimum Input Frequency (MHz) Maximum Input Frequency (MHz) 0.0672 (internal) 1.38 1.84 2.76 3.68 5.52 7.37 0.0576 IA3222/IA3223 0.0828 (internal) 2.0 2.667 4.0 5.333 8.0 10.667 0.08333 21 ...
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... APPLICATIONS Application Schematic IA3222B for worldwide telecom compliance Figure 23: Application schematic IA3222/IA3223 22 ...
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... Refer to the component discussion for more details. Note 4: C10 and C14 need to be NPO if V.90 modem performance is required. Otherwise more cost effective to use X7R ceramic capacitors. capacitors, drawn on PCB (Contact IAI for details.) IA3222/IA3223 23 ...
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... TBR21 current limit is no longer in force in Europe but may still be required for certain countries, e.g. Algeria, Bahrain, Croatia, Estonia, Ghana, Ivory Coast, Lebanon, Morocco and Turkey. This application is suitable for all other countries as well. Figure 24: Application schematic for legacy TBR21 current-limit support IA3222/IA3223 24 ...
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... This effect is less pronounced with components of larger size and higher voltage rating. Note 2: C10 and C14 need to be NPO if V.90 modem performance is required. Otherwise more cost effective to use X7R ceramic capacitors. capacitors, drawn on PCB (Contact IAI for details.) IA3222/IA3223 25 ...
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... Legacy TBR21 support is possible but not recommended since so few countries require it and the standard has been superseded. Current limiting is now obsolescent if not obsolete. In order to meet TBR21 current limit, a DAA needs to dissipate 2 W safely. In the IA3222/3223 application, about half of this power is dissipated in R3, R4, R10 and R11 and the other half in the NPN transistor. Figure 25: IA3222/3223 evaluation board ...
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... For optimal audio performance, minimize trace lengths between the System Side and its supply-decoupling capacitors. • Q2, Q3 and Q4 should be laid out with a lot of extra copper on both sides of the board with thermal vias in order to facilitate heat dissipation. Figure 26: IA3222/3223 evaluation board layout IA3222/IA3223 27 ...
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... All three pins TX, RX and ACREF may also be connected to codec using coupling capacitors. For the ACREF pin, a capacitor of at least 100nF is recommended. All coupling capacitors should be selected so that they will not cause any significant attenuation at low frequencies, taking input resistances into account. The TX pin is internally biased at 1.5V. Please contact Silicon Labs for additional assistance with interfacing the IA3223. IA3222/IA3223 28 ...
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... Rx - Figure 27: Single-ended interface 2k Tx Rx+ + Rx- - Figure 28: Differential interface — without reference Tx+ + Tx- - ACRef Rx+ + Rx- - 100nF Figure 29: Differential interface — with reference IA3222/IA3223 - To PWM converter + Transmitter HPF - 0.6V reference + From PWM converter Receiver LPF ACRef IA3223 ACRef IA3223 Rx 29 ...
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... In the on-hook state, the IA3222 Line Side chip converts the line voltage to a frequency at the rate of 2 kHz per Volt. The V-to-f’s operating range is from ±3V to over ±150V. This frequency is sent as pulses across the capacitor isolation barrier. The pulse duty cycle contains line-polarity information. The V-to-f converter’ ...
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... The IA3223 has a true line-polarity detector. Line polarity is directly sensed in the IA3222 Line-Side chip and this information is sent across the isolation barrier to the IA3223 System-Side chip. Line polarity reversal may take ms. ...
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... DC value of the received signal. This DC value is compared with short-term changes to detect loop current drops caused by a parallel phone on the line going off hook. Sensitivity to parallel pickup is also affected by the IA3222 Line-Side’s holding and AC-input capacitor values. There are four levels of parallel-pickup sensitivity, programmed by register bits LTH0 and LTH1. Each setting is about twice as sensitive as the previous ...
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... Drops over 500 ms indicate disconnect while shorter drops indicate call waiting. Consequently important to time the duration of line drops with at least 10 ms resolution. Line drop is detected by the IA3223 System Side and flagged as the LD (Line Drop) status bit when the IA3222 Line Side receives insufficient loop current to keep it operational (less than 10 mA). ...
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... Enable the current sensor. The loop current can now be read as incoming-data DC offset from the DC reference voltage. The sensitivity of the current sensor is approximately 1. offset for every loop current. Note that both the DC-offset correction factor and the gain change with the Line-Side termination impedance setting. IA3222/IA3223 34 ...
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... In other words, the power lines and the telephone cable form a very low impedance pulse transformer that may couple to the telephone line the IA3222/IA3223 RMS ...
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... The IA3222/3223 chipset does not need these costly EMI capacitors because of the high RF impedance of the isolation capacitors. These capacitors achieve an effective breakdown voltage in the tens only the cost of the PCB area they occupy. In practice, excessive common-mode voltage will arc across the surface of the board. If the DAA designer doesn’ ...
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... The IA3222 Line Side has a smart power-limiting hook control circuit that prevents damage to the hook switch; either during high voltage surges or even if continuous high voltage is present on the line. The chip senses both line voltage and line current. If the line voltage exceeds 100V or the loop current exceeds 170mA, the hook switch turns off to prevent excessive power dissipation in the main hook transistors ...
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... The reason is that opto-isolated systems need a gain of almost 100 on the transfer and servo photodiodes because of the typical 1 % current-transfer ratio. Normally, there is a small amount of isolation capacitance in the sensitive servo or transfer photodiode to the effect that at 3 kHz the common-mode balance may be 80dB or less. IA3222/IA3223 to AC ...
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... This results from the combination of very low isolation capacitance and internal filtering. Typically, RF immunity of the IA3222/3223 will be sufficient and the DAA will perform quite well without any special RF suppression components. On the other hand, if immunity is desired to the level specified in EN 55024 or even to Brazil’s more demanding Anexo a Resolução No 237, a pair of 470 pF high-voltage capacitors between Tip/Ring and the chassis ground is normally sufficient ...
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... All high-speed full-duplex modems (V.32, V.34, V.90 and V.92) during training build an exact line mirror (of what is left over from the DAA compromise hybrid) to cancel the echo to better than 70 dB. The IA3222 has a compromise trans-hybrid balance network on the Line Side that improves the dynamic range performance of the analog channel by minimizing the transmitted noise and distortion reflected back into the receiver channel ...
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... Trans-hybrid drift mostly arises from thermal effects due to heating of the Line Side both from the line current and the electronic environment. The IA3222 was designed to have very low thermal drift to minimize these effects. In telephony applications, hybrid return loss is heard as “sidetone”. Some sidetone is desirable as long not excessive in volume ...
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... PACKAGE INFORMATION QSOP-16 and QSOP-20 Packages MSOP-10 Package SOIC-8 Package (JEDEC Outline MS-012AA) IA3222/IA3223 42 ...
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... ORDERING INFORMATION IA3222/IA3223 DAA Chipset with Analog Interface DESCRIPTION IA3222A – Line Side US/Japan DAA IC IA3222B – Line Side Enhanced Worldwide DAA IC IA3223 – System Side Worldwide DAA IC IA3223A – System Side Worldwide DAA IC with pin hook control Silicon Labs, Inc. ...