ia3513 integration, ia3513 Datasheet
ia3513
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ia3513 Summary of contents
Page 1
... To protect valuable PCB “real-estate” in the target application, the IC has a small pin count because of the programmable I2C interface, rather than dedicated control pins. The IA3513 also includes a Clock Generation Block for increased flexibility; it generates both 26MHz and 32kHz output clocks. BLOCK DIAGRAM IA3513-DS Rev 1 ...
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... Battery Charger output A Codec Earphone Amplifier Positive Output A Codec Earphone Amplifier Negative Output Pwr Codec Positive Power Supply for decoupling (internally Generated) A Codec Microphone Bias Voltage I A Codec Microphone Amplifier Positive Input I A Codec Microphone Amplifier Negative Input Not Connected IA3513 2 ...
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... For detailed codec specifications, including supporting curves, see this document, appendix A. Symbol Avss-0 Vbat Avss-0.3 to Vbat + 0.3 < 5 Avss-0.3 to Vbat + 0.3 < 5 Avss-0.3 to Vbat + 0.3 < 5 Avss-0.3 to (Vbat + 0.3)< 3.6 Avss-0.3 to (Vbat + 0.3)< 3.6 TA AgndCodec VddCodec DAC MicBias ADC MicA Avss IA3513 Value Units V Avss-0 - ºC -55 to 125 ºC EAoutP Spk ...
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... The charger automatically starts charging cycles when the AC adaptor or USB are plugged-in, and shuts down when removed. Battery status monitor is included. Charge status is available through register read. Functional Block Diagram Charger Control Temperature FoldBack Control vCHARGER vBATo SCdac ctrl - + - + REF REF iBAT R1 IA3513 Bat 4 ...
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... JA JB JBA θ = Junction to ambient thermal resistance JA θ = Junction to board thermal resistance JB θ = Board to ambient thermal resistance JBA =14 Cº/W and θ Cº/ IA3513 Units ºC º ...
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... Battery Charger Flow Diagram IA3513 6 ...
Page 7
... FBTemp -FBHys Yes & FB Timer Expired FoldBack UP No Fold-Back Mode END Safety Mode Saffety Mode Yes Timer Start FoldBack DOWN RESTART FB TIMER Under or Over Voltage ? Saffety Mode Timed-Out Saffety Mode Conditions Still Safety Mode IA3513 Ibat = 0 Yes No Yes Yes No Met No END 7 ...
Page 8
... During the charging procedure, the IC temperature can increase to unsafe temperatures due to higher dropout in the pass- device. To allow charging with higher input voltages, IC temperature is monitored when it reaches FBTemp the charge current is lowered until a safe operating temperature is reached. This is not a mode per se, it operates in the constant current and constant voltage modes. Charge Profile IA3513 8 ...
Page 9
... During the shutdown time, everything except the output sensing comparator is disabled. Supply switch over-current protection is provided to protect the chip against overloads. Soft-start is provided by ramping up the internal reference from zero to the target value after power on reset. Top Level Block Diagram of the DC-DC Buck Converter IA3513 ...
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... Including Total IC Battery Current Internal Consumption 100% 90% 80% 70% 60% 50% 40% 30% 20% 0,001 0,01 Load Current (A) 4.1V Normal Mode 3.6V Normal Mode 4.1V FPWM Mode 3.6V FPWM Mode Load step 2mA to 20mA in forced PWM mode Output voltage 20mV/div Time scale 5ms/div IA3513 Units V mA MHz V mVrms % % 0,1 3.1V Normal Mode 3.1V FPWM Mode 10 ...
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... Load step 2mA to 40mA in forced PWM mode Output voltage 20mV/div Time scale 5ms/div Load step 2mA to 80mA in forced PWM mode Output voltage 20mV/div Time scale 5ms/div Load step 2mA to 40mA in forced PWM mode (zoom) Output voltage 50mV/div Time scale 200us/div IA3513 11 ...
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... IA3513 is in sleep mode. To shutdown the DC-DC the bit 7 of register 25 must be cleared. When this is done the DC-DC is shut down and the IA3513 enters sleep mode powering down all blocks, but still being able to start a charge or detect the on button push. ...
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... HOST SYSTEM RESET - CLK32POG Description The IA3513 has the ability to reset the host in order to enforce safe startup operation this the Clk32PoG pin of the IA3513 should be connected to the host reset pin. Startup The Clk32PoG pin stays low while the host supply voltage supplied by the IA3513 DC-DC is below 90% of its final value or the 32kHz clock is not available at the Clk32Out pin ...
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... SAD6 START GPIO5 CLPO32 Charge event with interruption acknowledged SCL SDA GPIO5 CLPO32 Charge event with interruption not acknowledged 2m s 90% (Frequency not to scale ) Startup slave AD0 INT ET FGRI CHI BTH2 ACK < 100 ms 100 ms IA3513 STOP slave BTH1 BTH0 ACK STOP ...
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... At the end of a calibration cycle, the new divider modulo is loaded into the divider to obtain the 32kHz output. 32kHz Oscillator Functional Block Diagram 26Mhz clock Internal LPO Calibration State Machine 32kHz Oscillator out Divider IA3513 15 ...
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... CLK 32kHz Calibration Calibration in sniff mode lib ra tio lib ra tio n Continuous mode calibration IA3513 ? lib ra tio fin ...
Page 17
... The 26 MHz crystal oscillator frequency can be trimmed using a 6bit word in register 23. The frequency adjustment is done by changing the IA3513 internal load capacitance array connected to pin MXclkin. The total trim capacitance is 3.465pF, and the LSB capacitance value is 55fF. For the midrange code the total capacitance is 9pF (Cl + Clt), in order to be compatible with the specification for the crystal typically used on the application ...
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... Clk26out clock output Generic Output Frequency Rise time 10%-90% Fall time 10%-90% Duty Cycle Phase noise at 10KHz Min Typ Max 32.768 30 70 -250 250 1 2 250 Min Typ Max 26 1 -121 IA3513 Units kHz % ppm ppm Units MHz dBc/Hz 18 ...
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... PCM_SYNC input. The internal clock generator adjusts to the correct ratios at startup. The PCM_OUT output is tri- stated when valid output data is not present. Timing Diagrams Data Transmit timing diagram for output on positive edge Data Transmit output on negative edge IA3513 19 ...
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... Delay from clock neg. edge to data off tDRS PCM data input setup time tDRH PCM data input hold time Data Receive Min Typ 125 1/(8 x 512) 1/(8 x 128 IA3513 16 LSB Max Unit 125 ...
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... The I2C address of the IA3513 is 1001111. The clock stretching functionality isn’t implemented in this slave, since it is not needed, because this is a relatively fast device. ...
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... SU.DAT DO.VAL t SU.STA D IN START Bus Timing Diagram Width Description (bits) 7 Slave address 8 Register address 8 Register data Timing Diagram for a Random Write IA3513 Max Unit 400 kHz µ s µ s 300 ns 300 0 245 ns 245 ...
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... Timing Diagram for a Sequential Read (start from Current Address Read) Note: Instead of a current address read, a random read may also precede a sequential read. slave slave AD7 AD0 D7 D0 ACK ACK START slave AD0 SAD6 SAD0 RD ACK START IA3513 STOP slave D7 D0 ACK STOP STOP slave master D7 D0 ACK no ACK STOP 23 ...
Page 24
... Blink mode (valid only for output hardware mode in GPIOS and 5), the GPIO will toggle continuously with on and off times set by register position. In this mode the GPIO state (high or low) written in the status register will be ignored. High Open Wake up Current Blink Drain input Open Drain • • • • • • IA3513 Charge Interruption notification Notification LED 24 ...
Page 25
... Upon a charger insertion (charge start) event (ACHP bit at 1), if the CHI interrupt is not acknowledged within a 100 ms time window, a reset will be issued to the host as described in further details in the Host System Reset section. Min Typ Max 4.242 (Battery Voltage) 2.75 (DC-DC output) 0.185 2.65 (DC-DC output) 2.25 1.5 1 0.5 25.5 13 220 IA3513 Units Ω Ω Ω 25 ...
Page 26
... To finalize the push button handling, the host acknowledges the interruption and the GPIO4 push/release notification by writing a ‘0’ to the bits INT and GPS4 of register 11, thus clearing the interruption and the sticky bit value. Then the whole cycle can be restarted. The operation of the DWN button is analogous. SCL SDA GPIO5 INT IA3513 HOST 26 ...
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... After the ISR finishes handling the GPIO2 interruption, it proceeds to acknowledge it, by clearing bits INT and GPS3 in register 11. Because there is no other pending interrupt, the GPIO5 interrupt notification pin goes low as illustrated in the next figure: slave AD0 INT DDB LB GPS1 GPS2 GPS3 ACK IA3513 STOP slave GPS4 GPS5 ACK STOP 27 ...
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... The following diagram illustrates what happens in the case that a new interrupt is generated on GPIO3, before the ISR acknowledges the previously detected sources (during the previous read). This next diagram shows what happens, when acknowledging the interrupts on ET, and GPS3, if there are no more pending interrupts. IA3513 28 ...
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... Res Res Res XTSD1 SDM RDE HP1 HP0 HPO R/W R/W R/W R/W R/W 0-> disabled 1->enabled IA3513 RDE HP1 HP0 HPO RDG0 RSTDF TDG1 TDG0 STG3 STG2 STG1 STG0 TOF3 TOF2 TOF1 TOF0 ROF3 ROF2 ROF1 ...
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... RDG0 RSTDF TDG1 R/W R/W R TAG0 STG3 STG2 STG1 R/W R/W R/W R TOF4 TOF3 TOF2 TOF1 R/W R/W R/W R/W R/W IA3513 D0 TDG0 0 R/W D0 STG0 0 R TOF0 0 R/W 30 ...
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... Battery Overvoltage (open) D[0] BUV Battery Undervoltage (short ROF4 ROF3 ROF2 ROF1 R/W R/W R/W R/W R THO Dc FBE ARS R/W R FBT Dc LCH BOV IA3513 D0 ROF0 0 R/W D0 ENC 1 R/W D0 BUV ...
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... Battery threshold selection for interrupt generation 4 bit selection range 3.15V PCM SFM FBB2 FBB1 FGB3 FGB2 FGB1 CHI BTH3 BTH2 BTH1 R/W R/W R/W R/W R/W IA3513 D0 FBB0 0 R step 12.5% D0 FGB0 BTH0 0 R/W 32 ...
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... GPS3 GPS4 R/W R/W R/W R/W R GPD1 GPD2 GPD3 GPD4 R/W R/W R/W R GOD2 GHD2 GOD3 GOD4 R/W R/W R/W R GPC1 GPC2 GPC3 GPC4 R/W R/W R/W R/W IA3513 D0 GPS5 0 R/W D0 GPD5 1 R/W D0 GOD5 0 R/W D0 GPC5 0 R/W 33 ...
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... GST2 GST3 GST4 R/W R/W R/W R GI1 GI2 GI3 GI4 R/W R/W R/W R/W R BON21 BON20 BOFF22 R/W R/W R/W R BON31 BON30 BOFF32 R/W R/W R/W R/W IA3513 D0 GST5 0 R/W D0 GI5 0 R BOFF21 BOFF20 0 1 R/W R BOFF31 BOFF30 0 1 R/W R/W 34 ...
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... R/W R/W R/W R BON51 BON50 BOFF52 R/W R/W R/W R EN1 EN0 EON1 EON0 R/W R/W R/W R GG0 MM1 MM0 R/W R/W R/W R/W IA3513 D1 D0 BOFF41 BOFF40 0 1 R/W R BOFF51 BOFF50 0 1 R/W R EOFF EOFF 0 1 R/W R ...
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... D3 D2 CRQ Res Res R/W R/W R/W R CPWM Res Res DCT2 R/W R/W R/W R HRC4 HRC3 HRC2 IA3513 D1 D0 Res Res 0 1 R/W R DCT1 DCT0 0 0 R/W R HRC1 HRC0 ...
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... SP5 SP4 SP3 SP2 R/W R/W R/W R/W Functions SP8 Res Res Res R/W R/W R/W R/W Functions IAC4 IAC3 IAC2 R/W R/W R/W R/W Functions IA3513 SP1 SP0 0 0 R/W R Res Res 0 0 R/W R IAC1 IAC0 0 0 R/W R/W 37 ...
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... Crystal Oscillator wake up delay selection: 00->8.65ms 01->4.35ms 10 -> 17.15ms 11->13ms. D[4:3] XTSD[1:0] This value needs to be updated only once after power delay value different than the default is needed. D[2:0] Res Reserved (must be kept at the default value Res XTSD1 XTSD0 Res R/W R/W R/W R/W Functions IA3513 D1 D0 Res Res 0 0 R/W R/W 38 ...
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... Agndcodec vCHARGER 1 26 PCM_SYNC GPIO1 2 25 PCM_CLK GPIO2 3 24 PCM_OUT GPIO3 4 23 Exposed PCM_IN SCLK Paddle 5 22 VddClkGen SDATA 6 21 MXclkin GPIO4 7 20 Clk26Rqst GPIO5 Battery IA3513 C9 C10 Battery C8 C11 C7 39 ...
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... PACKAGE INFORMATION RECOMMENDED PCB FOOTPRINT IA3513 40 ...
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... This page has been intentionally left blank. IA3513 41 ...
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... NO WARRANTIES OF ANY KIND, INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, ARE OFFERED IN THIS DOCUMENT. ©2008 Silicon Laboratories, Inc. All rights reserved. Silicon Laboratories is a trademark of Silicon Laboratories, Inc. All other trademarks belong to their respective owners. IA3513 42 ...