mk50h27 STMicroelectronics, mk50h27 Datasheet - Page 2
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mk50h27
Manufacturer Part Number
mk50h27
Description
Signalling System 7 Link Controller
Manufacturer
STMicroelectronics
Datasheet
1.MK50H27.pdf
(56 pages)
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MK50H27
INTRODUCTION (Continued)
and out of memory through the Host’s bus. A
possible system configuration for the MK50H27 is
shown in figure 1.
For added flexibility a transparent mode provides
an HDLC transport mechanism without link layer
support. In this mode no protocol processing is
done, all data received between opening flag and
CRC is written to the shared memory buffer and it
is up to the user to take care of the upper level
software.
DIP48 PIN CONNECTION (Top view)
2/56
BMO, BYTE, BUSREL
HOLD, BUSRQ
BMI, BUSAKO
VSS-GND
VSS-GND
ALE, AS
HLDA
READY
RESET
DAL07
DAL06
DAL05
DAL04
DAL03
DAL02
DAL01
DAL00
READ
INTR
DALI
DALO
DAS
CS
ADR
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
The MK50H27 may be used with any of several
popular microprocessors, such as: 68040 ...
68000, 6800, Z8000, Z80, 80486 ... 8086, i960,
etc.
The MK50H27 may be operated in either full or
half duplex mode. In half duplex mode, the RTS
and CTS modem control pins are provided. In full
duplex mode, these pins become user program-
mable I/O pins. All signal pins on the MK50H27
are TTL compatible. This has the advantage of
making the MK50H27 independent of the physical
interface. As shown in figure 1, line drivers and
receivers are used for electrical connection to the
physical layer.
M
K
5
0
H
2
7
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
VCC (+5V)
DAL08
DAL09
DAL10
DAL11
DAL12
DAL13
DAL14
DAL15
A16
A17
A18
A19
A20
A21
A22
A23
RD
DSR, CTS
TD
SYSCLK
RCLK
DTR, RTS
TCLK