mk50h27 STMicroelectronics, mk50h27 Datasheet - Page 26

• Manufacturer Part Number: mk50h27
• Description: Signalling System 7 Link Controller
• Manufacturer: STMicroelectronics

MK50H27
4.2.2 Timers
There are ten independent counter-timers defined in SS7. The upper 8 bits of IADR+02 are used
as a scaler for T1 through T7, and TP. The scaler is driven by a clock which is 1/32 of SYSCLK. N1 is
the maximum number of signal units allowed for retransmission (transmission window size) and N2 is the
maximum number of bytes allowed for retransmission. The value for N1 is set to 128.
The Host will write the period of N2, T1-T7, and TP into the Initialization Block.
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05
04
03
02:00
TIMER
SCALER
N2
T1
T2
LBACK
DRCK
DTCK
CKS
LBACK
0
4
5
6
7
Normal operation. No loopback.
Simple loopback. Receive data and clock are driven internally by transmit data and clock.
Transmit clock must be supplied externally
Clockless loopback. Receive data is driven internally by transmit data. Transmit and receive
clocks are driven by SYSCLK divided by 8.
Silent loopback. Same as simple loopback with td pin forced to all ones.
Silent clockless loopback. Combination of Silent and Clockless loopbacks. Receive data is
driven internally by transmit data, transmit and receive clocks are driven by SYSCLK divided
by 8. The TD pin is forced to all ones.
and check the CK field at the end of each signal unit. When
DRCK = 1, the receiver continues to extract the last 16 or 32 bits of
each signal unit, depending on CKS, but no check is performed to
determine whether the CK is correct. The CK is not stored into the
Receive buffer.
generate and append the CK to each signal unit. When DTCK = 1,
the CK logic is disabled, and no CK is generated with transmitted sig-
nal units. Setting DTCK=1 is useful in loopback testing for check-
ing the ability of the receiver to detect an incorrect CK.
32 bit CK is used.
configurations.
number.
clock pulses.
the prescaler is reset. This field is interpreted as the two’s comple-
ment of the prescaler period. The MK50H27 multiplies this value
by 16 when it is read into the device. Note: a prescale value of one
gives the smallest amount of scaling to the timers (512 clock pulses),
zero gives the largest (131584 clock pulses).
octets allowed for retransmission. N2 includes the opening and clos-
ing flags, BSN/BIB, FSN/FIB, LI, and the CK octets. This value is
expressed as a positive integer. Bits <14:8> of IADR + 02 represent
the most significant bits of N2.
time the MK50H27 will stay in the ALIGNED READY state before sig-
nalling link failure. Represented as two’s complement.
the MK50H27 will wait in the NOT ALIGNED state before signalling
link failure. Represented as two’s complement.
Disable Receiver CK. When DRCK = 0, the receiver will extract
Disable Transmitter CK. When DTCK = 0, the transmitter will
CK Select. When CKS = 1, the 16 bit CK is selected otherwise the
Loopback Control puts the MK50H27 into one of several loopback
DESCRIPTION
TIMER PRESCALER. Timers T1-T7 and TP are scaled by this
Octet window size. N2 gives the maximum number of MSU
ALIGNED READY TIMER PERIOD. T1 determines the maximum
NOT ALIGNED TIMER PERIOD. T2 determines the maximum time
The prescaler is incremented once every 32
When it reaches zero the timers are incremented and
DESCRIPTION
system