mk50h27 STMicroelectronics, mk50h27 Datasheet - Page 34

• Manufacturer Part Number: mk50h27
• Description: Signalling System 7 Link Controller
• Manufacturer: STMicroelectronics

MK50H27
4.3 Receive and Transmit Descriptor Rings
Each descriptor ring in memory is a 4 word entry. The following is the format of the receive and transmit
descriptors.
4.3.1 Receive Message Descriptor Entry
4.3.1.1 Receive Message Descriptor 0 (RMD0)
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BIT
15
14
13
12
11:08
11:10
07:00
NAME
OWNA
OWNB
SLF
ELF
0
PRIN
RBADR
1
5
O
W
N
A
1
4
O
W
N
B
1
3
S
L
F
PROCESSOR owns this descriptor. When this bit is a one the
MK50H27 owns this descriptor. The chip clears the OWNA bit af-
ter filling the buffer pointed to by the descriptor entry provided a valid
signal unit has been received. The Host sets the OWNA bit after
emptying the buffer. Once the MK50H27, Host, or I/O accelera-
tion processor has relinquished ownership of
change any field in the four words that comprise the descriptor entry.
bit. This bit is provided to facilitate use of a Layer 3 I/O processor.
by MK50H27 for this signal unit. It is used for data chaining buffers.
SLF is set by the MK50H27. NOTE: A ”Long Signal Unit” is any
MSU which needs data chaining.
MK50H27 for this signal unit. It is used for data chaining buffers. If
both SLF and ELF were set, the signal unit would fit into one buffer
and no data chaining would be required. ELF is set by the MK50H27.
received frame when JSS7E=1 (TTC JT-Q703 compliant mode).
This field is written by the Host and unchanged by MK50H27.
DESCRIPTION
When this bit is a zero either the HOST or the I/O ACCELERATION
This bit determines whether the Host or the Layer 3 I/O Processor owns
Start of Long Signal Unit indicates that this is the first buffer used
End of Long Signal Unit indicates that this the last buffer used by
Reserved, must be written as zeroes for CCITT/ITU compliant operation.
These bits indicate the content of the Priority Indication bits of the
The High Order 8 address bits of the buffer pointed to by this descriptor.
the buffer when OWNA is a zero.
1
2
E
L
F
1
1
PRIN
1
0
0
9
0
0
8
0
0
7
0
6
0
5
RBADR<23:16>
The MK50H27 never uses this
0
4
0
3
0
2
a buffer, it may not
0
1
0
0