mk50dn512zcll10 Freescale Semiconductor, Inc, mk50dn512zcll10 Datasheet

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... Freescale Semiconductor Data Sheet: Advance Information K50 Sub-Family Data Sheet Supports the following: MK50DX256ZCLL10, MK50DN512ZCLL10 Features • Operating Characteristics – Voltage range: 1.71 to 3.6 V – Flash write voltage range: 1.71 to 3.6 V – Temperature range (ambient): -40 to 85°C • Performance – 100 MHz ARM Cortex-M4 core with DSP instructions delivering 1 ...

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... DSPI switching specifications (low-speed mode)..57 6.8.5 DSPI switching specifications (high-speed mode) 59 6.8.6 I2C switching specifications..................................60 6.8.7 UART switching specifications..............................61 6.8.8 SDHC specifications.............................................61 6.8.9 I2S switching specifications..................................62 6.9 Human-machine interfaces (HMI)......................................64 6.9.1 TSI electrical specifications...................................64 7 Dimensions...............................................................................65 7.1 Obtaining package dimensions.........................................65 8 Pinout........................................................................................65 8.1 K50 Signal Multiplexing and Pin Assignments..................65 Preliminary Freescale Semiconductor, Inc. ...

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... K50 Pinouts.......................................................................70 K50 Sub-Family Data Sheet Data Sheet, Rev. 5, 5/2011. Freescale Semiconductor, Inc. 9 Revision History........................................................................71 Preliminary 3 ...

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... M = Fully qualified, general market flow • Prequalification • K50 • Cortex-M4 w/ DSP • Cortex-M4 w/ DSP and FPU • Program flash only • Program flash and FlexMemory Table continues on the next page... Preliminary and perform a part number Values Freescale Semiconductor, Inc. ...

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... Maximum CPU frequency (MHz) N Packaging type 2.4 Example This is an example part number: MK50DN512ZVMD10 3 Terminology and guidelines K50 Sub-Family Data Sheet Data Sheet, Rev. 5, 5/2011. Freescale Semiconductor, Inc. Description • • • 128 = 128 KB • 256 = 256 KB • 512 = 512 KB • 1M0 = 1 MB • ...

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... Definition: Attribute An attribute is a specified value or range of values for a technical characteristic that are guaranteed, regardless of whether you meet the operating requirements. K50 Sub-Family Data Sheet Data Sheet, Rev. 5, 5/2011. 6 Min. Max. 0.9 1.1 Min. Max. 10 130 Preliminary Unit V Unit µA Freescale Semiconductor, Inc. ...

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... Result of exceeding a rating Measured characteristic K50 Sub-Family Data Sheet Data Sheet, Rev. 5, 5/2011. Freescale Semiconductor, Inc. Min. — 7 Min. –0.3 1.2 The likelihood of permanent chip failure increases rapidly as soon as a characteristic begins to exceed one of its operating ratings. Operating rating ...

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... This is an example of an operating behavior that includes a typical value: K50 Sub-Family Data Sheet Data Sheet, Rev. 5, 5/2011. 8 Normal Limited operating operating range range - No permanent failure - No permanent failure - Correct operation - Possible decreased life - Possible incorrect operation Handling range - No permanent failure Preliminary Fatal range - Probable permanent failure ∞ Freescale Semiconductor, Inc. ...

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... Typical value conditions Typical values assume you meet the following conditions (or other conditions as specified): Symbol T Ambient temperature A V 3.3 V supply voltage DD 4 Ratings K50 Sub-Family Data Sheet Data Sheet, Rev. 5, 5/2011. Freescale Semiconductor, Inc. Min. Typ 1.00 1.05 1.10 V (V) DD Description Value 25 3.3 Preliminary Ratings Max ...

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... Min. -2000 -500 -100 Table continues on the next page... Preliminary Max. Unit Notes 150 °C 1 260 °C 2 245 Max. Unit Notes 3 — 1 Max. Unit Notes +2000 V 1 +500 V 2 +100 mA Min. Max. Unit –0.3 3.8 V — 185 mA –0.3 5.5 V Freescale Semiconductor, Inc. ...

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... V ≤ V ≤ 2 Input hysteresis HYS I Digital pin negative DC injection current — single pin ICDIO • V < V -0. K50 Sub-Family Data Sheet Data Sheet, Rev. 5, 5/2011. Freescale Semiconductor, Inc Min. 1.71 1.71 –0.1 –0.1 1.71 0.7 × 0.75 × — — 0.06 × V ...

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... TBD TBD TBD TBD TBD TBD TBD Table continues on the next page... Preliminary Max. Unit Notes mA — +5 — mA +25 — V — greater than V IN AIO_MIN Typ. Max. Unit Notes 1.1 TBD V 2.56 TBD V 2.70 TBD V 2.80 TBD V 2.90 TBD V 3.00 TBD 1.60 TBD V Freescale Semiconductor, Inc ...

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... V ≤ V ≤ 3 • 1.71 V ≤ V ≤ 2 Output low voltage — low drive strength • 2.7 V ≤ V ≤ 3 • 1.71 V ≤ V ≤ 2 K50 Sub-Family Data Sheet Data Sheet, Rev. 5, 5/2011. Freescale Semiconductor, Inc. Min. Typ. TBD 1.80 TBD 1.90 TBD 2.00 TBD 2.10 40 TBD 1.00 ...

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... VLLSx→RUN recovery times in the following table Min. — DD — — — — Table continues on the next page... Preliminary Max. Unit Notes 100 mA 1 μA 1 TBD μ μA 50 kΩ kΩ 3 Max. Unit Notes 300 μs 1 4.1 μs 123.8 μs 4.1 μs 49.3 μs Freescale Semiconductor, Inc. ...

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... Run mode current — all peripheral clocks DD_RUN_M enabled and peripherals active, code executing AX from flash • @ 1.8V • @ 3.0V • @ 25°C • @ 125°C K50 Sub-Family Data Sheet Data Sheet, Rev. 5, 5/2011. Freescale Semiconductor, Inc. Min. — — — — — — — — ...

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... TBD mA TBD mA TBD mA 6 TBD mA 7 TBD mA 8 TBD μA TBD μA TBD μA 9 TBD μA TBD μA TBD μA 9 TBD μA TBD μA TBD μA TBD μA TBD μA TBD μA TBD μA TBD μA TBD μA Freescale Semiconductor, Inc. ...

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... MCG in FEI mode (39.0625 kHz IRC), except for 1 MHz core (FBE) • All peripheral clocks disabled except FTFL • LVD disabled, USB regulator disabled • No GPIOs toggled • Code execution from flash K50 Sub-Family Data Sheet Data Sheet, Rev. 5, 5/2011. Freescale Semiconductor, Inc. Min. Typ. Max. — 0.7 TBD — ...

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... MCG in FEI mode (39.0625 kHz IRC), except for 1 MHz core (FBE) • All peripheral clocks enabled but peripherals are not in active operation • LVD disabled, USB regulator disabled • No GPIOs toggled • Code execution from flash K50 Sub-Family Data Sheet Data Sheet, Rev. 5, 5/2011. 18 Preliminary Freescale Semiconductor, Inc. ...

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... TEM Cell Method, and SAE Standard J1752-3, Measurement of Radiated Emissions from Integrated Circuits—TEM/ Wideband TEM (GTEM) Cell Method ° MHz (crystal OSC K50 Sub-Family Data Sheet Data Sheet, Rev. 5, 5/2011. Freescale Semiconductor, Inc. Frequency Typ. band (MHz) 0.15–50 TBD 50–150 TBD 150–500 TBD 500– ...

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... Normal run mode — 20 — — — — VLPR mode — — — Table continues on the next page... Preliminary Min. Max. Unit — — Max. Unit Notes 100 MHz — MHz 50 MHz 50 MHz 25 MHz 25 MHz 2 MHz 2 MHz 2 MHz Freescale Semiconductor, Inc. ...

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... V ≤ 3.6V DD • Slew enabled • 1.71 ≤ V ≤ 2.7V DD • 2.7 ≤ V ≤ 3. The greater synchronous and asynchronous timing must be met. K50 Sub-Family Data Sheet Data Sheet, Rev. 5, 5/2011. Freescale Semiconductor, Inc. Min. Max. — 1 — 25 Min. Max. 1.5 — 100 — ...

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... TBD resistance, junction to board Thermal TBD resistance, junction to case Thermal TBD characterization parameter, junction to package top outside center (natural convection) Preliminary Min. Max. Unit –40 125 °C –40 85 °C Unit Notes °C/W 1 °C/W 1 °C/W 1 °C/W 1 °C/W 2 °C/W 3 °C/W 4 Freescale Semiconductor, Inc. ...

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... Clock and data rise time r T Clock and data fall time f T Data setup s T Data hold h K50 Sub-Family Data Sheet Data Sheet, Rev. 5, 5/2011. Freescale Semiconductor, Inc. Peripheral operating requirements and behaviors Min. Frequency dependent 2 2 — — Preliminary Max. ...

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... K50 Sub-Family Data Sheet Data Sheet, Rev. 5, 5/2011 Table continues on the next page... Preliminary Ts Th Min. Max. Unit 2.7 3.6 V MHz 1/J1 — — — — ns — — — ns — — — — ns — Freescale Semiconductor, Inc. ...

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... TCLK low to TDO high-Z J13 TRST assert time J14 TRST setup time (negation) to TCLK high TCLK (input) K50 Sub-Family Data Sheet Data Sheet, Rev. 5, 5/2011. Freescale Semiconductor, Inc. Peripheral operating requirements and behaviors Figure 5. Test clock input timing Preliminary Min ...

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... K50 Sub-Family Data Sheet Data Sheet, Rev. 5, 5/2011 J11 J12 J11 Figure 7. Test Access Port timing Preliminary J5 J6 Input data valid Output data valid Output data valid J9 J10 Input data valid Output data valid Output data valid Freescale Semiconductor, Inc. ...

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... VDD and 25°C f Internal reference frequency (fast clock) — user intf_t trimmed K50 Sub-Family Data Sheet Data Sheet, Rev. 5, 5/2011. Freescale Semiconductor, Inc. Peripheral operating requirements and behaviors J14 Figure 8. TRST timing Table 15. MCG specifications Min. Typ. ...

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... MHz 3, 50 MHz 75 MHz 100 MHz — MHz 5, — MHz — MHz — MHz TBD ps TBD ps — — 100 MHz — µA 600 — µA — 4.0 MHz Freescale Semiconductor, Inc ...

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... This section provides the electrical characteristics of the module. 6.3.2.1 Oscillator DC electrical specifications Table 16. Oscillator DC electrical specifications Symbol Description V Supply voltage DD K50 Sub-Family Data Sheet Data Sheet, Rev. 5, 5/2011. Freescale Semiconductor, Inc. Peripheral operating requirements and behaviors Min. Typ. — 120 — 50 — ...

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... MΩ — MΩ — MΩ — MΩ — kΩ — kΩ — kΩ — kΩ Freescale Semiconductor, Inc. ...

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... Other frequency limits may apply when external clock is being used as a reference for the FLL or PLL 2. Proper PC board layout procedures must be followed to achieve specifications. K50 Sub-Family Data Sheet Data Sheet, Rev. 5, 5/2011. Freescale Semiconductor, Inc. Peripheral operating requirements and behaviors Min. ...

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... K50 Sub-Family Data Sheet Data Sheet, Rev. 5, 5/2011. 32 Min. Typ. 1.71 — — 100 — 2.5 — 15 — 0.6 Min. Typ. Max. — 32.768 — — 1000 — Preliminary Max. Unit 3.6 V — MΩ — pF — pF — V Unit Notes kHz ms 1 Freescale Semiconductor, Inc. ...

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... Assumes 25MHz flash clock frequency. 2. Maximum times for erase parameters based on expectations at cycling end-of-life. K50 Sub-Family Data Sheet Data Sheet, Rev. 5, 5/2011. Freescale Semiconductor, Inc. Peripheral operating requirements and behaviors Min. Typ. Max. — 20 TBD — ...

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... TBD — ≤ 125°C. j Min. 1.71 — — EZP_CK — 0 — Preliminary Unit mA Unit Notes years 2 years 2 years 2 cycles 3 Max. Unit 3 MHz SYS f /8 MHz SYS — ns — ns — ns — ns — — Freescale Semiconductor, Inc. ...

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... Data and FB_TA input setup FB5 Data and FB_TA input hold 1. Specification is valid for all FB_AD[31:0], FB_BE/BWEn, FB_CSn, FB_OE, FB_R/W,FB_TBST, FB_TSIZ[1:0], FB_ALE, and FB_TS. K50 Sub-Family Data Sheet Data Sheet, Rev. 5, 5/2011. Freescale Semiconductor, Inc. Peripheral operating requirements and behaviors EP3 EP2 EP4 EP9 ...

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... Specification is valid for all FB_AD[31:0], FB_BE/BWEn, FB_CSn, FB_OE, FB_R/W,FB_TBST, FB_TSIZ[1:0], FB_ALE, and FB_TS. 2. Specification is valid for all FB_AD[31:0] and FB_TA. K50 Sub-Family Data Sheet Data Sheet, Rev. 5, 5/2011. 36 Min. Max. 1.71 3.6 — TBD TBD — — 13.5 0 — 13.7 — 0.5 — Preliminary Unit Notes V MHz Freescale Semiconductor, Inc. ...

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... FB_A[Y] FB2 FB_D[X] Address FB_RW FB_TS FB_ALE FB_CSn FB_OEn FB_BEn FB_TA FB_TSIZ[1:0] Figure 10. FlexBus read timing diagram K50 Sub-Family Data Sheet Data Sheet, Rev. 5, 5/2011. Freescale Semiconductor, Inc. Peripheral operating requirements and behaviors FB3 FB5 Address FB4 Data AA=1 AA=0 FB4 FB5 AA=1 AA=0 TSIZ ...

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... FB_TA FB_TSIZ[1:0] Figure 11. FlexBus write timing diagram 6.5 Security and integrity modules There are no specifications necessary for the device's security and integrity modules. 6.6 Analog K50 Sub-Family Data Sheet Data Sheet, Rev. 5, 5/2011. 38 FB3 Address Data AA=1 AA=0 FB4 FB5 AA=1 AA=0 TSIZ Preliminary Freescale Semiconductor, Inc. ...

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... ADCK f ADC conversion ≤ 13 bit modes ADCK clock frequency f ADC conversion 16 bit modes ADCK clock frequency K50 Sub-Family Data Sheet Data Sheet, Rev. 5, 5/2011. Freescale Semiconductor, Inc. Peripheral operating requirements and behaviors Table 27 and Table 28 Min. 1 Typ. 1.71 — -100 ...

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... K50 Sub-Family Data Sheet Data Sheet, Rev. 5, 5/2011. 40 Min. 1 Max. Typ. 20.000 — 818.330 37.037 — 461.467 = 1.0 MHz unless otherwise stated. Typical values are for ADCK ADIN ADIN Preliminary Unit Notes 6 Ksps 7 Ksps / AS ADIN ADIN ADIN ADIN ADIN Freescale Semiconductor, Inc. ...

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... ENOB Effective number 16 bit differential mode of bits • Avg=32 • Avg=1 16 bit single-ended mode • Avg=32 • Avg=1 K50 Sub-Family Data Sheet Data Sheet, Rev. 5, 5/2011. Freescale Semiconductor, Inc. Peripheral operating requirements and behaviors = V REFH DDA 1 Min. Typ. 0.215 — 1.2 2 ...

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... DDA = 2.0 MHz unless otherwise stated. Typical values are for ADCK modes Preliminary = V ) (continued) SSA 2 Max. Unit Notes dB 5 TBD dB TBD dB 5 — dB — leakage current (refer to the MCU's voltage and current operating ratings) — mV/°C — mV Freescale Semiconductor, Inc. ...

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... Recommended ADC setting is: ADLSMP=1, ADLSTS MHz ADC clock. 7. ADC clock = 18 MHz, ADLSMP = 1, ADLST = 00, ADHSC = 1 8. ADC clock = 12 MHz, ADLSMP = 1, ADLST = 01, ADHSC = 1 K50 Sub-Family Data Sheet Data Sheet, Rev. 5, 5/2011. Freescale Semiconductor, Inc. Peripheral operating requirements and behaviors Min. 1 Max. Typ. ...

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... VDDA 60Hz — 500mVpp, — 50Hz, VCM 100Hz TBD mV Output offset = V *(Gain+1) OFS 10 µs 5 TBD ppm/° 50°C TBD ppm/°C TBD ppm/° 50°C, ADC Averaging=32 TBD %/V V from 1.71 DDA to 3.6V TBD %/V Freescale Semiconductor, Inc. ...

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... Between IN+ and IN-. The PGA draws a DC current from the input terminals. The magnitude of the DC current is a strong function of input common mode voltage (V 4. Gain = 2 PGAG 5. After changing the PGA gain setting, a minimum of 2 ADC+PGA conversions should be ignored. K50 Sub-Family Data Sheet Data Sheet, Rev. 5, 5/2011. Freescale Semiconductor, Inc. Peripheral operating requirements and behaviors Min. 1 Typ. I × ...

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... DD Preliminary Typ. Max. Unit — 3.6 V — 200 μA — 20 μA — — — — — — mV — — V — 0 200 ns 250 600 ns — 40 μs 7 — μA — 0.5 3 LSB — 0.3 LSB Freescale Semiconductor, Inc. ...

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... Figure 15. Typical hysteresis vs. Vin level (VDD=3.3V, PMODE=0) K50 Sub-Family Data Sheet Data Sheet, Rev. 5, 5/2011. Freescale Semiconductor, Inc. Peripheral operating requirements and behaviors 1 1.3 1.6 1.9 2.2 Vin level (V) Preliminary HYSTCTR S etting 2.5 2.8 3.1 47 ...

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... A small load capacitance (47 pF) can improve the bandwidth performance of the DAC K50 Sub-Family Data Sheet Data Sheet, Rev. 5, 5/2011 1.3 1.6 1.9 2.2 Vin level (V) Min. 1.71 1.13 −40 — — Preliminary HYSTCTR Setting 2.5 2.8 3.1 Max. Unit Notes 3 105 °C 100 Freescale Semiconductor, Inc. ...

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... The INL is measured for 0+100mV The DNL is measured for 0+100 The DNL is measured for 0+100mV Calculated by a best fit curve from V K50 Sub-Family Data Sheet Data Sheet, Rev. 5, 5/2011. Freescale Semiconductor, Inc. Peripheral operating requirements and behaviors Min. — — ...

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... Peripheral operating requirements and behaviors 6. VDDA = 3.0V, reference select set for VDDA (DACx_CO:DACRFS = 1), high power mode(DACx_C0:LPEN = 0), DAC set to 0x800, Temp range from -40C to 105C Figure 17. Typical INL error vs. digital code K50 Sub-Family Data Sheet Data Sheet, Rev. 5, 5/2011. 50 Preliminary Freescale Semiconductor, Inc. ...

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... Input offset current (0–50° Input offset current (-40–105° Input bias current (0–50°C) BIAS K50 Sub-Family Data Sheet Data Sheet, Rev. 5, 5/2011. Freescale Semiconductor, Inc. Peripheral operating requirements and behaviors Min. 1.71 — — — — — — ...

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... MHz — — MHz 90 — dB — TBD pF — TBD Ω — TBD V ±0.5 — — — deg TBD — μs TBD — μs 350 TBD nV/√Hz 90 TBD nV/√Hz Max. Unit Notes 3 -1.4 V DDA 100 pf Freescale Semiconductor, Inc. ...

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... Voltage noise density (noise floor) 1kHz Vn Voltage noise density (noise floor) 10kHz Figure 19. Typical Open Loop Gain vs. Frequency [TBD] Figure 20. Typical Phase vs. Frequency [TBD] K50 Sub-Family Data Sheet Data Sheet, Rev. 5, 5/2011. Freescale Semiconductor, Inc. Peripheral operating requirements and behaviors Min. Typ. Max. — ...

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... Notes 3 -1.4 V DDA 50 C 100 pf Max. Unit Notes TBD mV TBD μV/C TBD pA TBD pA 1500 Ω @ 100kHz, High speed mode — kΩ — dB — dB — V/μs — V/μs — MHz — MHz — dB — dB — deg Max. Unit Notes 3.6 V Freescale Semiconductor, Inc. ...

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... Table 42. VREF limited-range operating behaviors Symbol Description V Voltage reference output with factory trim out TBD Figure 21. Typical output vs.temperature K50 Sub-Family Data Sheet Data Sheet, Rev. 5, 5/2011. Freescale Semiconductor, Inc. Peripheral operating requirements and behaviors Min. Max. −40 105 — 100 Min. ...

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... K50 Sub-Family Data Sheet Data Sheet, Rev. 5, 5/2011. 56 Figure 22. Typical output vs. VDD Min. TBD 0 14.25 0.25 Min. 2.7 — Table continues on the next page... Preliminary Typ. Max. Unit TBD TBD V — 2 μA 100 150 μA — 24.8 kΩ TBD 0.4 V Typ. Max. Unit Notes — 5.5 V 120 TBD μA Freescale Semiconductor, Inc. ...

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... Operating voltage Frequency of operation DS1 DSPI_SCK output cycle time DS2 DSPI_SCK output high/low time DS3 DSPI_PCSn valid to DSPI_SCK delay K50 Sub-Family Data Sheet Data Sheet, Rev. 5, 5/2011. Freescale Semiconductor, Inc. Peripheral operating requirements and behaviors Min. Typ. — 1 — 500 — ...

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... Last data Description Preliminary Max. Unit Notes — — ns — ns — ns DS4 Min. Max. Unit 1.71 3.6 V — 6.25 MHz — ns BUS (t / SCK SCK/2) — — — — ns — — Freescale Semiconductor, Inc. ...

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... DSPI_SIN to DSPI_SCK input setup DS8 DSPI_SCK to DSPI_SIN input hold 1. The delay is programmable in SPIx_CTARn[PSSCK] and SPIx_CTARn[CSSCK]. 2. The delay is programmable in SPIx_CTARn[PASC] and SPIx_CTARn[ASC]. K50 Sub-Family Data Sheet Data Sheet, Rev. 5, 5/2011. Freescale Semiconductor, Inc. Peripheral operating requirements and behaviors DS10 DS15 DS12 First data ...

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... Data DS14 First data Data Preliminary DS4 Min. Max. Unit 2.7 3.6 V 12.5 MHz — ns BUS (t /2) − SCK SCK — — — — ns — — DS9 DS16 DS11 Last data Last data Freescale Semiconductor, Inc. ...

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... SDHC input / card inputs SDHC_CMD, SDHC_DAT (reference to SDHC_CLK) SD7 t SDHC input setup time ISU SD8 t SDHC input hold time IH K50 Sub-Family Data Sheet Data Sheet, Rev. 5, 5/2011. Freescale Semiconductor, Inc. Peripheral operating requirements and behaviors Min. 2.7 Card input clock — ...

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... Figure 27. SDHC timing master (clocks driven) and slave 2 S master mode timing Preliminary Min. Max. Unit 2.7 3 SYS 45% 55% MCLK period — ns SYS 45% 55% BCLK period — -2.5 — ns — — — — ns Freescale Semiconductor, Inc. ...

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... I2S_FS input hold after I2S_BCLK S15 I2S_BCLK to I2S_TXD/I2S_FS output valid S16 I2S_BCLK to I2S_TXD/I2S_FS output invalid S17 I2S_RXD setup before I2S_BCLK S18 I2S_RXD hold after I2S_BCLK K50 Sub-Family Data Sheet Data Sheet, Rev. 5, 5/2011. Freescale Semiconductor, Inc. Peripheral operating requirements and behaviors ...

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... Table continues on the next page... Preliminary S16 S14 S16 Max. Unit Notes 3.6 V 500 pF 1 TBD MHz 2 TBD MHz 3 TBD pF TBD mV 4 TBD μ TBD μ TBD % 6 TBD % 7 TBD % 8 — fF/count 9 — fF/count 10 16 bits 25 μs 11 Freescale Semiconductor, Inc. ...

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... The following table shows the signals available on each pin and the locations of these pins on the devices supported by this document. The Port Control Module is responsible for selecting which ALT functionality is available on each pin. K50 Sub-Family Data Sheet Data Sheet, Rev. 5, 5/2011. Freescale Semiconductor, Inc. Min. Typ. — ...

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... K50 Sub-Family Data Sheet Data Sheet, Rev. 5, 5/2011. 66 ALT1 ALT2 ALT3 ALT4 SPI1_PCS1 UART1_TX SDHC0_D1 SPI1_SOUT UART1_RX SDHC0_D0 SPI1_SCK UART1_CTS SDHC0_DCL _b K SPI1_SIN UART1_RTS SDHC0_CM _b D PTE4 SPI1_PCS0 UART3_TX SDHC0_D3 PTE5 SPI1_PCS2 UART3_RX SDHC0_D2 Preliminary ALT5 ALT6 ALT7 EzPort I2C1_SDA I2C1_SCL Freescale Semiconductor, Inc. ...

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... TSI0_CH4 SWD_DIO 43 PTA4 NMI_b/ TSI0_CH5 EZP_CS_b 44 PTA12 CMP2_IN0 CMP2_IN0 45 PTA13 CMP2_IN1 CMP2_IN1 46 PTA14 DISABLED K50 Sub-Family Data Sheet Data Sheet, Rev. 5, 5/2011. Freescale Semiconductor, Inc. ALT1 ALT2 ALT3 ALT4 PTA0 UART0_CTS FTM0_CH5 _b PTA1 UART0_RX FTM0_CH6 PTA2 UART0_TX FTM0_CH7 PTA3 UART0_RTS FTM0_CH0 _b ...

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... FTM0_CH0 _b PTC2 SPI0_PCS2 UART1_CTS FTM0_CH1 _b Preliminary ALT5 ALT6 ALT7 EzPort I2S0_RXD LPT0_ALT1 FTM1_QD_P HA FTM1_QD_P HB FTM0_FLT3 FTM0_FLT0 FB_AD20 FB_AD19 FTM0_FLT1 FB_AD18 FTM0_FLT2 FB_AD17 EWM_IN FB_AD16 EWM_OUT_ b FB_AD15 FTM2_QD_P HA FTM2_QD_P HB FB_AD31 CMP0_OUT FB_AD30 CMP1_OUT FB_AD29 CMP2_OUT FB_AD28 FB_AD14 FB_AD13 FB_AD12 Freescale Semiconductor, Inc. ...

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... VDD VDD 90 PTC16 91 PTC17 92 PTC18 93 PTD0 94 PTD1 /ADC0_SE5b /ADC0_SE5b PTD1 95 PTD2 96 PTD3 K50 Sub-Family Data Sheet Data Sheet, Rev. 5, 5/2011. Freescale Semiconductor, Inc. ALT1 ALT2 ALT3 ALT4 PTC3 SPI0_PCS1 UART1_RX FTM0_CH2 PTC4 SPI0_PCS0 UART1_TX FTM0_CH3 PTC5 SPI0_SCK LPT0_ALT2 PTC6 SPI0_SOUT PDB0_EXTR ...

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... K50 Sub-Family Data Sheet Data Sheet, Rev. 5, 5/2011. 70 ALT1 ALT2 ALT3 ALT4 PTD4 SPI0_PCS1 UART0_RTS FTM0_CH4 _b SPI0_PCS2 UART0_CTS FTM0_CH5 _b SPI0_PCS3 UART0_RX FTM0_CH6 PTD7 CMT_IRO UART0_TX FTM0_CH7 Preliminary ALT5 ALT6 ALT7 EzPort FB_AD2 EWM_IN FB_AD1 EWM_OUT_ b FB_AD0 FTM0_FLT0 FTM0_FLT1 Freescale Semiconductor, Inc. ...

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... VREFL 23 VSSA 24 ADC1_SE16/OP1_OUT/CMP2_IN2/ 25 ADC0_SE22/OP0_DP2/OP1_DP2 Figure 30. K50 100 LQFP Pinout Diagram 9 Revision History The following table provides a revision history for this document. K50 Sub-Family Data Sheet Data Sheet, Rev. 5, 5/2011. Freescale Semiconductor, Inc. Preliminary Revision History 75 VDD 74 VSS PTC3 73 72 PTC2 PTC1 ...

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... K50 Sub-Family Data Sheet Data Sheet, Rev. 5, 5/2011. 72 Table 53. Revision History footnote in "Voltage and Current Operating Requirements" table. IC spec in "Power consumption operating behaviors" table DD_VBAT description and specs in "USB VREG electrical specifications" table LIM Preliminary Freescale Semiconductor, Inc. ...

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... For further information, see http://www.freescale.com or contact your Freescale sales representative. For information on Freescale's Environmental Products program http://www.freescale.com/epp. Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © 2010–2011 Freescale Semiconductor, Inc. ...