mk50dn512zcll10 Freescale Semiconductor, Inc, mk50dn512zcll10 Datasheet - Page 59
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mk50dn512zcll10
Manufacturer Part Number
mk50dn512zcll10
Description
K50 Sub-family Data Sheet Supports The Following
Manufacturer
Freescale Semiconductor, Inc
Datasheet
1.MK50DN512ZCLL10.pdf
(73 pages)
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6.8.5 DSPI switching specifications (high-speed mode)
The DMA Serial Peripheral Interface (DSPI) provides a synchronous serial bus with
master and slave operations. Many of the transfer attributes are programmable. The tables
below provide DSPI timing characteristics for classic SPI timing modes. Refer to the
DSPI chapter of the Reference Manual for information on the modified transfer formats
used for communicating with slower peripheral devices.
1. The delay is programmable in SPIx_CTARn[PSSCK] and SPIx_CTARn[CSSCK].
2. The delay is programmable in SPIx_CTARn[PASC] and SPIx_CTARn[ASC].
Freescale Semiconductor, Inc.
Num
DS1
DS2
DS3
DS4
DS5
DS6
DS7
DS8
DSPI_SS
DSPI_SCK
(CPOL=0)
DSPI_SOUT
DSPI_SIN
Operating voltage
Frequency of operation
DSPI_SCK output cycle time
DSPI_SCK output high/low time
DSPI_PCSn valid to DSPI_SCK delay
DSPI_SCK to DSPI_PCSn invalid delay
DSPI_SCK to DSPI_SOUT valid
DSPI_SCK to DSPI_SOUT invalid
DSPI_SIN to DSPI_SCK input setup
DSPI_SCK to DSPI_SIN input hold
Table 47. Master mode DSPI timing (high-speed mode)
Figure 24. DSPI classic SPI timing — slave mode
K50 Sub-Family Data Sheet Data Sheet, Rev. 5, 5/2011.
Description
DS13
DS15
First data
First data
DS14
Preliminary
DS10
DS12
Data
Data
(t
(t
(t
SCK
BUS
BUS
2 x t
Peripheral operating requirements and behaviors
TBD
Min.
2.7
−2
—
—
/2) − 2
2
2
0
x 2) −
x 2) −
BUS
DS11
DS9
(t
Last data
Last data
SCK
Max.
3.6
8.5
25
—
—
—
—
—
—
/2) + 2
DS16
MHz
Unit
ns
ns
ns
ns
ns
ns
ns
ns
V
Notes
1
2
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