mk50dn512zcll10 Freescale Semiconductor, Inc, mk50dn512zcll10 Datasheet - Page 62

• Manufacturer Part Number: mk50dn512zcll10
• Description: K50 Sub-family Data Sheet Supports The Following
• Manufacturer: Freescale Semiconductor, Inc

Peripheral operating requirements and behaviors
6.8.9 I
This section provides the AC timings for the I
modes (clocks input). All timings are given for non-inverted serial clock polarity
(TCR[TSCKP] = 0, RCR[RSCKP] = 0) and a non-inverted frame sync (TCR[TFSI] = 0,
RCR[RFSI] = 0). If the polarity of the clock and/or the frame sync have been inverted, all
the timings remain valid by inverting the clock signal (I2S_BCLK) and/or the frame sync
(I2S_FS) shown in the figures below.
62
Num
S10
S1
S2
S3
S4
S5
S6
S7
S8
S9
SDHC_CLK
Output SDHC_CMD
Output SDHC_DAT[3:0]
Input SDHC_CMD
Input SDHC_DAT[3:0]
2
S switching specifications
Operating voltage
I2S_MCLK cycle time
I2S_MCLK pulse width high/low
I2S_BCLK cycle time
I2S_BCLK pulse width high/low
I2S_BCLK to I2S_FS output valid
I2S_BCLK to I2S_FS output invalid
I2S_BCLK to I2S_TXD valid
I2S_BCLK to I2S_TXD invalid
I2S_RXD/I2S_FS input setup before I2S_BCLK
I2S_RXD/I2S_FS input hold after I2S_BCLK
Description
K50 Sub-Family Data Sheet Data Sheet, Rev. 5, 5/2011.
Table 50. I
SD3
SD6
Figure 27. SDHC timing
SD2
2
S master mode timing
SD7
Preliminary
2
S in master (clocks driven) and slave
SD8
SD1
2 x t
5 x t
45%
45%
Min.
-2.5
2.7
20
—
—
-3
0
SYS
SYS
Freescale Semiconductor, Inc.
Max.
55%
55%
3.6
15
15
—
—
—
—
—
MCLK period
BCLK period
Unit
ns
ns
ns
ns
ns
ns
ns
ns
V