lm49350rl National Semiconductor Corporation, lm49350rl Datasheet - Page 47

• Manufacturer Part Number: lm49350rl
• Description: High Performance Audio Codec Sub-system With A Ground-referenced Stereo Headphone Amplifier & An Ultra Low Emi Class D Loudspeaker Amplifier With Dual I2s/pcm Digital Audio Interfaces
• Manufacturer: National Semiconductor Corporation

21.0 ADC Control Registers
This register is used to control the LM49350's ADC:
Bits
Bits
7:0
6.4
0
1
2
3
7
ADC_DSP_ONLY
ADC_CLK_DIV
ADC_CLK_SEL
MUTE_R
MUTE_L
MONO
Field
Field
OSR
This programs the half cycle divider that preceeds the ADC. The input of this divider should be
around 12MHz. The default of this divider is 0x00.
Program this divider with the division you want, multiplied by 2, and subtract 1.
This sets mono or stereo operation of the ADC.
This sets the oversampling ratio of the ADC.
If set, a digital mute is applied to the Left (or mono) ADC output.
If set, a digital mute is applied to the Right ADC output.
This selects the source of the ADC clock domain, ADC_SOURCE_CLK.
If set the ADC's analog circuitry is disabled to reduce power consumption, however, ADC DSP
functionality is maintained. This can be used to perform asyncronous resampling between audio
rates of a common family. Setting this bit is also useful whenever applying Automatic Level Control
(ALC) to an analog only audio path.
MONO
OSR
0
1
0
1
TABLE 28. ADC_CLK_DIV (0x21h)
TABLE 27. ADC Basic (0x20h)
ADC_CLK_SEL
ADC_CLK_DIV
00000000
00000001
00000010
00000011
11111101
11111110
11111111
000
001
010
011
100
—
Oversampling Ratio
Mono Voice (Right ADC channel disabled, Left ADC channel active)
Stereo Audio ADC
47
128
64
Description
Description
ADC Operation
Mono Voice ADC Oversampling Ratio
Stereo Audio
PORT1_RX_CLK
PORT2_RX_CLK
PLL1_OUTPUT2
PLL2_OUTPUT
Divides by
Source
MCLK
127.5
125
128
127
128
1.5
—
1
1
2
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