clc1003 Cadeka Microcircuits LLC., clc1003 Datasheet - Page 14

• Manufacturer Part Number: clc1003
• Description: Low Distortion, Low Offset, Rrio Amplifer
• Manufacturer: Cadeka Microcircuits LLC.

Data Sheet
The first place to start is to determine the source resis-
tance. If it is very small an additional resistance may need
to be added to keep the values of R
levels. For this analysis we assume that R
sistance present on the non-inverting input. This gives us
one equation that we must solve:
This equation can be rearranged to solve for R
The other consideration is desired gain (G) which is:
By plugging in the value for R
And R
The complete input offset equation is now only dependent
on the voltage offset and input offset terms given by:
And the output offset is:
Noise analysis
The complete equivalent noise circuit is shown in Figure 7.
The complete noise equation is given by:
©2004-2008 CADEKA Microcircuits LLC
v
2
o
=
+
–
v
2
orext
g
+ –
Figure 7: Complete Equivalent Noise Circuit
can be written in terms of R
+ e
VO
+ –
R
VI
g
OS
n
OS
1 +
R
+ –
= G ∗
R
g
R
=
g
RG
RF
g
= (R
= (G * R
G = (1 + R
( )
V
R
R
2
IO
( )
t
t
f
V
+ i
= Rg||Rf
* R
= G * R
IO
2
bp
+
–
+ I
f
CLC1003
2
g
t
R
) / (R
∗ RT 1 +
) / (G - 1)
f
(
+ I
we get
f
OS
/R
(
t
OS
g
+ –
∗ RT
f
t
)
- R
and G as follows:
f
∗ RT
RG
RF
and R
t
)
)
2
)
t
2
2
is the total re-
+ i
g
(
g
to practical
R
bn
:
L
∗ RF
)
2
Where V
is given by:
The complete equation can be simplified to:
It’s easy to see that the effect of amplifier voltage noise
is proportionate to gain and will tend to dominate at large
gains. The other terms will have their greatest impact at
large R
Layout Considerations
General layout and supply bypassing play major roles in
high frequency performance. CADEKA has evaluation
boards to use as a guide for high frequency layout and as
aid in device testing and characterization. Follow the steps
below as a basis for high frequency layout:
• Include 6.8µF and 0.1µF ceramic capacitors for power
supply decoupling
• Place the 6.8µF capacitor within 0.75 inches of the power pin
• Place the 0.1µF capacitor within 0.1 inches of the power pin
• Remove the ground plane under and around the part,
especially near the input and output pins to reduce para-
sitic capacitance
• Minimize all trace lengths to reduce series inductances
Refer to the evaluation board layouts below for more in-
formation.
Evaluation Board Information
The following evaluation boards are available to aid in the
testing and layout of these devices:
CEB002
CEB003
Evaluation Board
t
v
2
o
values at lower gains.
orext
v
2
o
= 3 ∗ 4kT ∗ G ∗ RT
= e
is the noise due to the external resistors and
(
n
1 +
#
RG
RF
CLC1003 in SOT23-5
CLC1003 in SOIC-8
2
)
+ e
+ e
( )
Products
G
n
G
∗
2
RG
RF
+ 2 ∗ i
www.cadeka.com
2
(
+ e
n
∗ RT
2
F
)
2
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