clc1005iso8x Cadeka Microcircuits LLC., clc1005iso8x Datasheet - Page 12

• Manufacturer Part Number: clc1005iso8x
• Description: Low Cost, +2.7v To 5.5v, 260mhz Rail-to-rail Amplifers
• Manufacturer: Cadeka Microcircuits LLC.

Data Sheet
Application Information
General Description
The CLC1005, CLC1015, and CLC2005 are single supply,
general purpose, voltage-feedback amplifiers fabricated
on a complementary bipolar process using a patent pend-
ing topography. They feature a rail-to-rail output stage
and is unity gain stable. Both gain bandwidth and slew
rate are insensitive to temperature.
The common mode input range extends to 300mV below
ground and to 1.2V below V
will not cause phase reversal. However, if the input volt-
age exceeds the rails by more than 0.5V, the input ESD
devices will begin to conduct. The output will stay at the
rail during this overdrive condition.
The design uses a Darlington output stage. The output
stage is short circuit protected and offers “soft” saturation
protection that improves recovery time.
Figures 1, 2, and 3 illustrate typical circuit configurations for
non-inverting, inverting, and unity gain topologies for dual
supply applications. They show the recommended bypass
capacitor values and overall closed loop gain equations.
Figure 4 shows the typical non-inverting gain circuit for
single supply applicaitons.
©2004-2009 CADEKA Microcircuits LLC
Input
Figure 1. Typical Non-Inverting Gain Circuit
R
g
+
-
+V
-V
s
s
6.8μF
0.1μF
0.1μF
6.8μF
s
. Exceeding these values
R
f
G = 1 + (R
R
L
f
/R
Output
g
)
At non-inverting gains other than G = +1, keep R
1kΩ to minimize peaking; thus, for optimum response at a
gain of +2, a feedback resistor of 1kΩ is recommended.
Figure 5 illustrates the CLC1005, CLC1015, and CLC2005
frequency response with both 1kΩ and 2kΩ feedback
resistors.
Figure 4. Single Supply Non-Inverting Gain Circuit
Input
Input
Figure 2. Typical Inverting Gain Circuit
In
R
R
Figure 3. Unity Gain Circuit
1
g
R
+
-
+
g
-
+V
-V
+V
-V
-
+
s
s
s
+V
s
6.8μF
0.1μF
0.1μF
6.8μF
6.8μF
0.1μF
0.1μF
6.8μF
s
0.01µF
6.8μF
+
R
f
R
f
G = - (R
For optimum input offset
voltage set R
G = 1
Out
www.cadeka.com
f
R
/R
L
g
Output
R
)
1
L
= R
Output
f
|| R
g
g
below
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