clc1010 Cadeka Microcircuits LLC., clc1010 Datasheet - Page 9
![no-image](/images/no-image-200.jpg)
clc1010
Manufacturer Part Number
clc1010
Description
70?a, Low Cost, +2.7v & +5v, 7.3mhz Rail-to-rail Amplifers
Manufacturer
Cadeka Microcircuits LLC.
Datasheet
1.CLC1010.pdf
(15 pages)
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
clc1010ISO8X
Manufacturer:
CADEKA
Quantity:
20 000
Advance Data Sheet
Application Information
General Description
The CLC1010 family are a single supply, general purpose,
voltage-feedback amplifiers fabricated on a complementary
bipolar process. The CLC1010 offers 7.3MHz unity gain
bandwidth, 9V/μs slew rate, and only 70μA supply current.
It features a rail-to-rail output stage and is unity gain stable.
The design utilizes a patent pending topology that provides
increased slew rate performance. The common mode input
range extends to 300mV below ground and to 1.2V below
Vs. Exceeding these values will not cause phase reversal.
However, if the input voltage exceeds the rails by more
than 0.5V, the input ESD devices will begin to conduct. The
output will stay at the rail during this overdrive condition.
The design uses a Darlington output stage. The output
stage is short circuit protected and offers “soft” saturation
protection that improves recovery time.
Figures 1, 2, and 3 illustrate typical circuit configurations for
non-inverting, inverting, and unity gain topologies for dual
supply applications. They show the recommended bypass
capacitor values and overall closed loop gain equations.
Figure 4 shows the typical non-inverting gain circuit for
single supply applicaitons.
©2009 CADEKA Microcircuits LLC
Input
Figure 1. Typical Non-Inverting Gain Circuit
R
g
+
-
+V
-V
s
s
6.8μF
0.1μF
0.1μF
6.8μF
R
f
G = 1 + (R
R
L
f
/R
Output
g
)
Figure 4. Single Supply Non-Inverting Gain Circuit
Input
Input
Figure 2. Typical Inverting Gain Circuit
In
R
R
Figure 3. Unity Gain Circuit
1
g
R
+
-
+
g
-
+V
-V
+V
-V
-
+
s
s
s
+V
s
6.8μF
0.1μF
0.1μF
6.8μF
6.8μF
0.1μF
0.1μF
6.8μF
s
0.01µF
6.8μF
+
R
f
R
f
G = - (R
For optimum input offset
voltage set R
G = 1
Out
www.cadeka.com
f
R
/R
L
g
Output
R
)
1
L
= R
Output
f
|| R
g
9