74aup1t45 NXP Semiconductors, 74aup1t45 Datasheet - Page 27

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74aup1t45

Manufacturer Part Number
74aup1t45
Description
Low-power Dual Supply Translating Transceiver; 3-state
Manufacturer
NXP Semiconductors
Datasheet

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NXP Semiconductors
74AUP1T45_1
Product data sheet
13.3 Power-up considerations
13.4 Enable times
A proper power-up sequence always should be followed to avoid excessive supply
current, bus contention, oscillations, or other anomalies. Take the following precautions to
guard against such power-up problems:
Calculate the enable times for the 74AUP1T45 using the following formulas:
In a bidirectional application, these enable times provide the maximum delay from the time
the DIR bit is switched until an output is expected. For example, if the 74AUP1T45 initially
is transmitting from A to B, then the DIR bit is switched, the B port of the device must be
disabled before presenting it with an input. After the B port has been disabled, an input
signal applied to it appears on the corresponding A port after the specified propagation
delay.
Connect ground before any supply voltage is applied.
Power-up V
V
t
t
t
t
PZH
PZL
PZH
PZL
CC(B)
(DIR to A) = t
(DIR to B) = t
(DIR to A) = t
(DIR to B) = t
can be ramped up along with or after V
CC(A)
.
PHZ
PHZ
Rev. 01 — 18 October 2006
PLZ
PLZ
(DIR to B) + t
(DIR to B) + t
(DIR to A) + t
(DIR to A) + t
Low-power dual supply translating transceiver; 3-state
PLH
PHL
PLH
PHL
(B to A)
(B to A)
(A to B)
(A to B)
CC(A)
.
74AUP1T45
© NXP B.V. 2006. All rights reserved.
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