at49lh00b4 ATMEL Corporation, at49lh00b4 Datasheet

at49lh00b4

Manufacturer Part Number

at49lh00b4

Description

4-megabit Top Boot, Bottom Partitioned Firmware Hub And Low-pin Count Flash Memory

Manufacturer

ATMEL Corporation

Datasheet

1.AT49LH00B4.pdf (41 pages)

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Features

•

1. Description

The AT49LH00B4 is a Flash memory device designed for use in PC and notebook

BIOS applications. The device complies with version 1.1 of Intel’s LPC Interface Spec-

ification, providing support for both FWH and LPC memory read and write cycles. The

device can also automatically detect the memory cycle type to allow the AT49LH00B4

to be used as a FWH with Intel chipsets or as an LPC Flash with non-Intel chipsets.

The sectoring of the AT49LH00B4’s memory array has been optimized to meet the

needs of today’s BIOS applications. By optimizing the size of the sectors, the BIOS

code memory space can be used more efficiently. Because certain BIOS code mod-

ules must reside in their own sectors by themselves, the wasted and unused memory

space that occurred with previous generation BIOS Flash memory devices can be

greatly reduced. This increased memory space efficiency allows additional BIOS rou-

tines to be developed and added while still maintaining the same overall device

density.

Complies with Intel

Auto-detection of FWH and LPC Memory Cycles

Top Boot with Bottom Partitioned Memory Array for Efficient Vital Data Storage

Two Configurable Interfaces

FWH/LPC Interface

A/A Mux Interface

Single Voltage Operation

Industry-Standard Package Options

Green (Pb/Halide-free) Packaging Option

– Supports both Firmware Hub (FWH) and LPC Memory Read and Write Cycles

– Can Be Used as FWH for Intel 8xx, E7xxx, and E8xxx Series Chipsets

– Can Be Used as LPC Flash for Non-Intel Chipsets

– 64-Kbyte Top Boot Sector, Six 64-Kbyte Sectors, One 32-Kbyte Sector, One

– Or Memory Array Can Be Divided Into Eight Uniform 64-Kbyte Sectors for Erasing

– FWH/LPC Interface for In-System Operation

– Address/Address Multiplexed (A/A Mux) Interface for Programming during

– Operates with the 33 MHz PCI Bus Clock

– 5-signal Communication Interface Supporting Byte Reads and Writes

– Two Hardware Write Protect Pins: TBL for Top Boot Sector and WP for All

– Five General-purpose Input (GPI) Pins for System Design Flexibility

– Identification (ID) Pins for Multiple Device Selection

– Sector Locking Registers for Individual Sector Read and Write Protection

– 11-pin Multiplexed Address and 8-pin Data Interface

– Facilitates Fast In-System or Out-of-System Programming

– 3.0V to 3.6V Supply Voltage for Read and Write Operations

– 32-lead PLCC

– 40-lead TSOP

16-Kbyte Sector, Two 8-Kbyte Sectors

Manufacturing

Other Sectors

Low-Pin Count (LPC) Interface Specification Revision 1.1

4-megabit

Top Boot,

Bottom

Partitioned

Firmware Hub

and Low-Pin

Count Flash

Memory

AT49LH00B4

3379C–FLASH–3/05

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