m36w0r5020b0 STMicroelectronics, m36w0r5020b0 Datasheet
m36w0r5020b0
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m36w0r5020b0 Summary of contents
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... Random Access: 70ns DUAL OPERATIONS – Program Erase in one Bank while Read in others – No delay between Read and Write operations December 2004 M36W0R5020T0 M36W0R5020B0 Figure 1. Package FBGA Stacked TFBGA88 (ZAQ) BLOCK LOCKING – All blocks locked at Power-up – Any combination of blocks can be locked – ...
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... M36W0R5020T0, M36W0R5020B0 TABLE OF CONTENTS FEATURES SUMMARY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 FLASH MEMORY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Figure 1. Package SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 SUMMARY DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Figure 2. Logic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Table 1. Signal Names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Figure 3. TFBGA Connections (Top view through package SIGNAL DESCRIPTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Address Inputs (A0-A20 Data Input/Output (DQ0-DQ15 Flash Chip Enable (E ).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 F Flash Output Enable (G ) ...
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... Figure 17. Stacked TFBGA88 8x10mm - 8x10 active ball array, 0.8mm pitch, Package Outline . . 23 Table 12. Stacked TFBGA88 8x10mm - 8x10 active ball array, 0.8mm pitch, Mechanical Data . . 23 PART NUMBERING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Table 13. Ordering Information Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 REVISION HISTORY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Table 14. Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 M36W0R5020T0, M36W0R5020B0 S Controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 ...
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... M36W0R5020T0, M36W0R5020B0 SUMMARY DESCRIPTION The M36W0R5020T0 and M36W0R5020B0 com- bine two memory devices in a Multi-Chip Package: a 32-Mbit, Multiple Bank Flash memory, the M58WR032FT/B and a 4-Mbit SRAM. Recommended operating conditions do not allow more than one memory to be active at the same time. The memory is offered in a Stacked TFBGA88 (8 x 10mm, 8x10 ball array, 0 ...
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... A3 D A17 DQ8 DQ0 M36W0R5020T0, M36W0R5020B0 A19 DDF PPF A20 DQ2 DQ10 DQ5 ...
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... M36W0R5020T0, M36W0R5020B0 SIGNAL DESCRIPTIONS See Figure 2., Logic Diagram and Names, for a brief overview of the signals connect this device. Address Inputs (A0-A20). Addresses are common inputs for the Flash memory and SRAM components. The other lines (A18-A20) are inputs for the Flash memory component only. ...
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... If V PPF voltage range ( DDQ PPF trol input. In this case a voltage lower than V M36W0R5020T0, M36W0R5020B0 ). The Lower gives an absolute protection against program or erase, while V (see Tables evant values). V ning of a program or erase; a change in its value after the operation has started does not have any effect and program or erase operations continue ...
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... M36W0R5020T0, M36W0R5020B0 FUNCTIONAL DESCRIPTION The Flash memory and SRAM components have separate power supplies but share the same grounds. They are distinguished by three Chip En- able inputs: E for the Flash memory and for the SRAM. S Recommended operating conditions do not allow more than one device to be active at a time. The Figure 4 ...
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... SRAM Standby Note Don't care can be tied the valid address has been previously latched Depends WAIT signal polarity is configured using the Set Configuration Register command. Refer to M58WR032FT/B datasheet for details. M36W0R5020T0, M36W0R5020B0 ( WAIT ...
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... FLASH MEMORY COMPONENT The M36W0R5020T0 and M36W0R5020B0 con- tain a 32 Mbit Flash memory. For detailed informa- tion on how to use it, see the M58WR032FT/B SRAM COMPONENT The M36W0R5020T0 and M36W0R5020B0 con- tain a 4 Mbit SRAM. See Figure 5., SRAM Block Diagram in conjunction with the Figure 5 ...
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... UB and/ ing edge whichever occurs first. The tim- S M36W0R5020T0, M36W0R5020B0 ings are referenced to the signal that terminates the Write cycle. The outputs are disabled during Write cycles (whenever E1 The Write AC Waveforms are shown in Figures 11, 12, ...
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... M36W0R5020T0, M36W0R5020B0 MAXIMUM RATING Stressing the device above the rating listed in the Absolute Maximum Ratings table may cause per- manent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the Operating sections of this specification is not im- Table 3 ...
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... Table 5. Device Capacitance Symbol Parameter C Input Capacitance IN C Output Capacitance OUT Note: Sampled only, not 100% tested. M36W0R5020T0, M36W0R5020B0 Conditions summarized in AC Measurement check that the operating conditions in their circuit match the operating conditions when relying on the quoted parameters. Flash Memory Min Max 1.7 1.95 – ...
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... M36W0R5020T0, M36W0R5020B0 Table 6. Flash Memory DC Characteristics - Currents Symbol Parameter I Input Leakage Current LI I Output Leakage Current LO Supply Current Asynchronous Read (f=6MHz) Supply Current Synchronous Read (f=54MHz) I DD1 Supply Current Synchronous Read (f=66MHz) I Supply Current (Reset) DD2 I Supply Current (Standby) DD3 I Supply Current (Automatic Standby) ...
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... Standby Current DDS DD I Supply Current DD V Input Low Voltage IL V Input High Voltage IH V Output Low Voltage OL V Output High Voltage OH M36W0R5020T0, M36W0R5020B0 Test Condition Min –0.5 V –0.4 DDQ I = 100µ –100µA V –0.1 OH DDQ Program, Erase 1.1 Program, Erase 11 ...
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... M36W0R5020T0, M36W0R5020B0 Figure 8. SRAM Read Mode AC Waveforms, Address Controlled with UB A0-A17 DQ0-DQ15 DATA VALID Note Low High Low Figure 9. SRAM Read AC Waveforms, G A0-A17 DQ0-DQ15 Note means both UB and Write Enable ( High. Address Valid prior the same time Figure 10 ...
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... Chip Enable 1 High or Chip Enable 2 Low to Power Down t PD (1) Chip Enable 1 Low or Chip Enable 2 High to Power Note: 1. Sampled only. Not 100% tested. 2. Whatever the temperature and voltage, t less than t . GHDX M36W0R5020T0, M36W0R5020B0 Parameter and t are less than t and t E1HDZ E2LDZ E1LDX M36W0R5020T0, M36W0R5020B0 Unit Min ...
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... M36W0R5020T0, M36W0R5020B0 Figure 11. SRAM Write AC Waveforms, E1 A0-A17 tGHDZ Note 2 DQ0-DQ15 Note and UB ,LB must be asserted to initiate a write cycle The I/O pins are in output mode and input signals should not be applied ...
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... The I/O pins are in output mode and input signals should not be applied and W are deasserted at the same time, DQ0-DQ15 remain high impedance means both UB and M36W0R5020T0, M36W0R5020B0 Controlled, G High during Write S S tAVAV VALID tAVWH tE1LWH tE2HWH tAVWL tWLWH tBLWH tDVWH INPUT VALID ...
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... M36W0R5020T0, M36W0R5020B0 Figure 13. SRAM Write AC Waveforms, W A0-A17 tAVWL W S DQ0-DQ15 Note 1 Note: 1. During this period, the I/O pins are in output mode and input signals should not be applied and W are deasserted at the same time, DQ0-DQ15 remain high impedance. ...
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... WHDZ (1) t Write Enable Low to Output Hi-Z t HZWE WLDZ t WLWH t WLE1H t Write Enable Pulse Width PWE t WLE2L t WLBH Note: 1. Whatever the temperature and voltage, t M36W0R5020T0, M36W0R5020B0 M36W0R5020T0, M36W0R5020B0 Parameter is less than t . WLDZ WHDX Unit Min Max ...
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... M36W0R5020T0, M36W0R5020B0 Figure 15. SRAM Low V Data Retention AC Waveforms, E1 DDS V DDS Figure 16. SRAM Low V Data Retention AC Waveforms, E2 DDS V DDS V DDS (min Table 11. SRAM Low V Data Retention Characteristic DDS Symbol Parameter Supply Current I DDDR (Data Retention) Supply Voltage ...
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... A1 A2 0.850 b 0.350 D 8.000 D1 5.600 ddd E 10.000 E1 7.200 E2 8.800 e 0.800 FD 1.200 FE 1.400 FE1 0.600 SD 0.400 SE 0.400 M36W0R5020T0, M36W0R5020B0 Min Max Typ 1.200 0.200 0.0335 0.300 0.400 0.0138 7.900 8.100 0.3150 0.2205 0.100 9.900 10.100 0.3937 0.2835 0.3465 – ...
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... M36W0R5020T0, M36W0R5020B0 PART NUMBERING Table 13. Ordering Information Scheme Example: Device Type M36 = Multi-Chip Package (Flash + RAM) Flash 1 Architecture W = Multiple Bank, Burst mode Flash 2 Architecture 0 = none present Operating Voltage 1.7 to 1.95V DDF DDQ DDP Flash 1 Density Mbit Flash 2 Density 0 = none present ...
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... Flash memory technology replaced by the 0.13µm technology. 06-May-2004 2.0 Package specifications updated. E and F Lead-free Package options added to 13., Ordering Information Document status promoted to full Datasheet. 17-Dec-2004 3.0 Flash memory and PSRAM data updated. TFBGA88 package fully compliant with the ST ECOPACK specification. M36W0R5020T0, M36W0R5020B0 Revision Details Scheme. Table 25/26 ...
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... M36W0R5020T0, M36W0R5020B0 Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice ...