m36w0r5020b0 STMicroelectronics, m36w0r5020b0 Datasheet - Page 4

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m36w0r5020b0

Manufacturer Part Number
m36w0r5020b0
Description
32 Mbit 2mb X16, Multiple Bank, Burst Flash Memory And 4 Mbit Sram, 1.8v Supply Multi-chip Package
Manufacturer
STMicroelectronics
Datasheet
M36W0R5020T0, M36W0R5020B0
SUMMARY DESCRIPTION
The M36W0R5020T0 and M36W0R5020B0 com-
bine two memory devices in a Multi-Chip Package:
Recommended operating conditions do not allow
more than one memory to be active at the same
time.
The memory is offered in a Stacked TFBGA88
(8 x 10mm, 8x10 ball array, 0.8mm pitch) pack-
age.
In addition to the standard version, the package is
also available in Lead-free version, in compliance
with JEDEC Std J-STD-020B, the ST ECOPACK
7191395 Specification, and the RoHS (Restriction
of Hazardous Substances) directive. All packages
are compliant with Lead-free soldering processes.
The memory supplied with all the bits erased (set
to ‘1’).
Figure 2. Logic Diagram
4/26
A0-A20
a 32-Mbit, Multiple Bank Flash memory, the
M58WR032FT/B
and a 4-Mbit SRAM.
WP
RP
W
UB
E1
E2
LB
G
E
G
W
L
K
F
F
F
F
S
S
S
F
F
F
S
S
S
21
V
DDF
M36W0R5020T
M36W0R5020B
V
DDQ
V SS
V
PPF
V
DDS
16
DQ0-DQ15
WAIT
AI08754b
F
Table 1. Signal Names
Note: 1. A20-A18 are address inputs for the Flash memory com-
A0-A20
DQ0-DQ15
V
V
V
V
V
NC
DU
Flash Memory
L
E
G
W
RP
WP
K
WAIT
SRAM
E1
G
W
UB
LB
F
DDF
DDQ
PPF
SS
DDS
F
F
F
S
F
S
S
S
F
S
F
, E2
F
ponent only.
S
(1)
Address Inputs
Common Data Input/Output
Flash Memory Power Supply
Common Flash and SRAM Power
Supply for I/O Buffers
Common Flash Optional Supply
Voltage for Fast Program and Erase
Ground
SRAM Power Supply
Not Connected Internally
Do Not Use as Internally Connected
Latch Enable input
Chip Enable input
Output Enable input
Write Enable input
Reset input
Write Protect input
Burst Clock
Wait Data in Burst Mode
Chip Enable input
Output Enable input
Write Enable input
Upper Byte Enable input
Lower Byte Enable input

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