xc1765d Xilinx Corp., xc1765d Datasheet

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xc1765d

Manufacturer Part Number
xc1765d
Description
Qpro Family Of Xc1700d Qml Configuration Proms
Manufacturer
Xilinx Corp.
Datasheet

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DS070 (v2.1) June 1, 2000
Features
DS070 (v2.1) June 1, 2000
Product Specification
Certified to MIL-PRF-38535 Appendix A QML
(Qualified Manufacturer Listing.)
Also available under the following Standard Microcircuit
Drawings (SMD): 5962-94717 and 5962-95617.
Configuration one-time programmable (OTP) read-only
memory designed to store configuration bitstreams of
Xilinx FPGA devices
On-chip address counter, incremented by each rising
edge on the clock input
Simple interface to the FPGA requires only one user
I/O pin
Cascadable for storing longer or multiple bitstreams
Programmable reset polarity (active High or active
Low) for compatibility with different FPGA solutions
Low-power CMOS EPROM process
Available in 5V version only
Programming support by leading programmer
manufacturers.
Design support using the Xilinx Alliance and
Foundation series software packages.
© 2000 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at http://www.xilinx.com/legal.htm.
All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.
RESET/
RESET
OE/
OE
or
Figure 1: Simplified Block Diagram (does not show programming circuit)
CLK
CE
R
V CC
V PP
GND
0
0
www.xilinx.com
1-800-255-7778
Address Counter
2
EPROM
Matrix
Cell
QPRO Family of XC1700D QML
Configuration PROMs
Product Specification
Description
The XC1700D QPRO™ family of configuration PROMs pro-
vide an easy-to-use, cost-effective method for storing Xilinx
FPGA configuration bitstreams.
When the FPGA is in Master Serial mode, it generates a
configuration clock that drives the PROM. A short access
time after the rising clock edge, data appears on the PROM
DATA output pin that is connected to the FPGA D
FPGA generates the appropriate number of clock pulses to
complete the configuration. Once configured, it disables the
PROM. When the FPGA is in Slave Serial mode, the PROM
and the FPGA must both be clocked by an incoming signal.
Multiple devices can be concatenated by using the CEO
output to drive the CE input of the following device. The
clock inputs and the DATA outputs of all PROMs in this
chain are interconnected. All devices are compatible and
can be cascaded with other members of the family.
For device programming, either the Xilinx Alliance™ or the
Foundation™ series development systems compiles the
FPGA design file into a standard HEX format which is then
transferred to most commercial PROM programmers.
Output
TC
OE
CEO
DATA
DS027_01_021500
IN
pin. The
1

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xc1765d Summary of contents

Page 1

R DS070 (v2.1) June 1, 2000 Features • Certified to MIL-PRF-38535 Appendix A QML (Qualified Manufacturer Listing.) • Also available under the following Standard Microcircuit Drawings (SMD): 5962-94717 and 5962-95617. • Configuration one-time programmable (OTP) read-only memory designed to store ...

Page 2

... XC4000 series 95,008 to 247,968 XQ4005E XQ4010E XQ4013E www.xilinx.com 1-800-255-7778 R . Failure 8-pin Configuration Bits 36,288 65,536 131,072 262,144 PROM XC1765D to XC17128D XC17128D to XC17256D 95,008 XC17128D 178,144 XC17256D 247,968 XC17256D DS070 (v2.1) June 1, 2000 Product Specification ...

Page 3

R Controlling PROMs Connecting the FPGA device with the PROM. • The DATA output(s) of the PROM(s) drives the D input of the lead FPGA device. • The Master FPGA CCLK output drives the CLK input(s) of the PROM(s). • ...

Page 4

QPRO Family of XC1700D QML Configuration PROMs Vcc DOUT FPGA MODES* RESET RESET CCLK DONE * For mode pin connections, refer to the appropriate FPGA data sheet. (Low Resets the Address Pointer) CCLK (Output) DIN DOUT (Output) Figure 2: Master ...

Page 5

R Standby Mode The PROM enters a low-power standby mode whenever CE is asserted High. The output remains in a high impedance state regardless of the state of the OE input. Table 1: Truth Table for XC1700 Control Inputs Control ...

Page 6

... QPRO Family of XC1700D QML Configuration PROMs XC1736D, XC1765D, XC17128D and XC17256D Absolute Maximum Ratings Symbol V Supply voltage relative to GND CC V Supply voltage relative to GND PP V Input voltage relative to GND IN V Voltage applied to High-Z output TS T Storage temperature (ambient) STG T Maximum soldering temperature (10s @ 1/16 in.) ...

Page 7

... DS070 (v2.1) June 1, 2000 Product Specification QPRO Family of XC1700D QML Configuration PROMs (1,2) T SCE CAC Description (3) (3,4) = 0.0V and V = 3.0V www.xilinx.com 1-800-255-7778 T SCE T HCE T HOE T CYC DS027_03_021500 XC1736D XC17128D XC1765D XC17256D Min Max Min Max - 150 - 200 - ...

Page 8

... Float delays are measured with loads. Transition is measured at ±200mV from steady state active levels CDF Last Bit T OCK T OCE Description (3,4) (3) = 0.0V and V = 3.0V www.xilinx.com 1-800-255-7778 (1,2) First Bit T OOE T OCE DS027_04_021500 XC1736D XC17128D XC1765D XC17256D Min Max Min Max - DS070 (v2.1) June 1, 2000 Product Specification R Units ns ...

Page 9

... DD8 = 8-pin Ceramic DIP www.xilinx.com 1-800-255-7778 Operating Range/Processing M = Military (T = –55° to +125° Military (T = –55° to +125°C) C QML certified to MIL-PRF-38535 XC1765DDD8M 5962-9471701MPA Operating Range/Processing M = Military (T = –55° to +125° Military (T = –55° to +125°C) C QML certified to MIL-PRF-38535 Revision ...

Page 10

QPRO Family of XC1700D QML Configuration PROMs 10 www.xilinx.com 1-800-255-7778 R DS070 (v2.1) June 1, 2000 Product Specification ...

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