tza3019 NXP Semiconductors, tza3019 Datasheet - Page 9

• Manufacturer Part Number: tza3019
• Description: 2.5 Gbits/s Dual Postamplifier With Level Detectors And 2 X 2 Switch
• Manufacturer: NXP Semiconductors

Philips Semiconductors
FUNCTIONAL DESCRIPTION
The TZA3019 is a dual postamplifier with multiplexer and
loss of signal detection (see Figs 1, 2 and 3). The RF path
starts with the multiplexer, which connects an amplifier to
one of the two inputs. It is possible to invert the output for
easy layout of the Printed-Circuit Board (PCB). The signal
is amplified to a certain level. To guarantee this level with
minimum distortion over the temperature range and level
range, an active control part is added. The offset
compensation circuit following the inverter minimizes the
offset.
The Received Signal Strength Indicator (RSSI) or the Loss
Of Signal (LOS) detector uses a 7-stage ‘successive
detection’ circuit. It provides a logarithmic output. The LOS
detector is followed by a comparator with a programmable
threshold. The input signal level-detection is implemented
to check if the input signal voltage is above the user
programmed level. This can insure that data will only be
transmitted when the input signal-to-noise ratio is sufficient
for low bit error rate system operation. A second
offset compensation circuit minimizes the offset of the
logarithmic amplifier.
RF input circuit
The input circuit contains internal 50
decoupled to V
capacitor (see Fig.6).
The input pins are DC-biased at approximately
V
TZA3019 can be DC-coupled, but AC-coupling is
preferred. In case of DC-coupling, the driving source must
operate within the allowable input range
(V
than a few millivolts should be avoided, since the internal
DC-offset compensation circuit has a limited correction
range. When AC-coupling is used, if no DC-compatibility is
required, the values of the coupling capacitors must be
large enough to pass the lowest input frequency of
interest. Capacitor tolerance and resistor variation must be
included for an accurate calculation. Do not use signal
frequencies around the low cut-off circuit frequencies
(f
for the LOS circuits).
RF output circuit
Matching the main amplifier outputs (see Fig.7) is not
mandatory. In most applications, the transmission line
receiving end will be properly matched, while very little
reflections occur.
2001 Jun 25
CC
CC
3dB(l)
2.5 Gbits/s dual postamplifier with level
detectors and 2
0.33 V by an internal reference generator. The
1.0 V to V
= 50 kHz for the postamplifiers and f
CC
CC
via an internal common mode 12 pF
+ 0.3 V). A DC-offset voltage of more
2 switch
resistors
3dB(l)
= 1 MHz
9
Matching the transmitting end to absorb reflections is only
recommended for very sensitive applications.
In such cases, pull-up resistors of 100
connected as close as possible to the IC from pins OUT1
and OUT1Q, and pins OUT2 and OUT2Q to GND1B and
GND2B respectively. These matching resistors are not
needed in most applications.
Postamplifier level adjustment
The postamplifier boosts the signal up to PECL levels. The
output can be either CML- or PECL-level compatible,
adjusted by means of the voltage on pins LEVEL1
and LEVEL2. The DC voltages of pins OUT1 and OUT1Q,
and pins OUT2 and OUT2Q match with the DC-levels
on pins LEVEL1 and LEVEL2, respectively. Due to the
receiving end 50
same level of V
AC-coupling are not equal to V
DC-coupling (see Figs 7 and 8).
When pin LEVEL1 or LEVEL2 is connected to V
connected, the postamplifier is in power-down state
(see Fig.7).
Postamplifier DC offset cancellation loop
Offset control loops connected between the inputs of the
buffers A1A and A2A and the outputs of the amplifiers A1B
and A2B (see Figs 1, 2 and 3) will keep the input of both
buffers at their toggle point during the absence of an input
signal. The active offset compensation circuit is integrated,
so no external capacitor is required. The loop time
constant determines the lower cut-off frequency of the
amplifier chain. The cut-off frequency of the offset
compensations is fixed internally at approximately 5 kHz.
handbook, halfpage
IN1Q, IN2Q
IN1, IN2
o(p-p)
Fig.6 RF input circuit.
load resistance, it means that at the
, V
12 pF
50
LEVEL1
420
and V
50
LEVEL1
LEVEL2
Product specification
MGS555
and V
should be
TZA3019
with
LEVEL2
V CC1A,
V CC2A
GND1A,
GND2A
CC
with
or not