tza3005 NXP Semiconductors, tza3005 Datasheet - Page 10

• Manufacturer Part Number: tza3005
• Description: Sdh/sonet Stm1/oc3 And Stm4/oc12 Transceiver
• Manufacturer: NXP Semiconductors

Philips Semiconductors
Signal Detect TTL (SDTTL)
This is a TTL signal with an internal pull-up resistor. It is
active HIGH when SDPECL is unconnected (logic 0),
active LOW when SDPECL is at logic 1. This single-ended
TTL input is driven by the external optical receiver module
to indicate a loss of received optical power. When SDTTL
is inactive, the data on RXSD and RXSDQ will be internally
forced to a constant zero. When SDTTL is active, data on
the RXSD and RXSDQ pins will be processed normally.
Table 5 SDPECL/SDTTL truth table
C
Bus width selection (BUSWIDTH)
This TTL signal is used to select 4-bit or 8-bit operation for
the transmit and receive parallel interfaces. LOW selects a
4-bit bus width. HIGH selects an 8-bit bus width.
Reference clock (REFCLK and REFCLKQ)
These differential PECL inputs supply the reference clock
for the internal bit clock frequency synthesizer.
Diagnostic loopback enable (DLEN)
This active LOW TTL input selects diagnostic loopback.
When DLEN is HIGH, the TZA3005 uses the primary data
(RXSD) and clock (RXSCLK) inputs. When LOW, the
TZA3005 uses the diagnostic loopback clock and data
from the transmitter.
Master reset (MRST)
This is an active LOW TTL level reset input. SYNCLKDIV
does not toggle during reset.
Line loopback enable (LLEN)
This active LOW TTL input selects line loopback. When
LLEN is LOW, the TZA3005 will route the data from the
RXSD and RXSCLK inputs to the TXSD and TXSCLK
outputs.
1997 Aug 05
OMMON INPUT SIGNALS
0 or floating
0 or floating
SDH/SONET STM1/OC3 and
STM4/OC12 transceiver
SDPECL
1
1
1 or floating
1 or floating
SDTTL
0
0
RXPD OUTPUT DATA
RXSD input data
RXSD input data
0
0
10
Reference select (REFSEL0 and REFSEL1)
This TTL signal is used to select the reference clock
frequency (see Table 3).
Mode select (MODE)
This TTL signal is used to select the serial bit rate.
LOW selects 155.52 Mbits/s. HIGH selects
622.08 Mbits/s.
Test inputs (STOPSYN, STOPTX, STOPRX and RSTRX)
These active HIGH TTL signals are used to test internal
circuitry during production testing. All must be LOW during
normal operation. Internal pull-down resistors will hold all
four test pins LOW if not connected.
T
Transmit clock outputs (TXSCLK and TXSCLKQ)
This differential PECL transmit serial clock output can be
used to retime the TXSD signal. The clock will be
622.08 MHz or 155.52 MHz depending on the operating
mode.
Transmit Serial Data (TXSD and TXSDQ)
These differential PECL serial data stream signals are
normally connected to an optical transmitter module or to
the TZA3001 laser driver.
Parallel clock (SYNCLKDIV)
This CMOS reference clock is generated by dividing the
internal bit clock by eight (or by four when BUSWIDTH is
LOW). It is normally used to coordinate byte-wide transfers
between upstream logic and the TZA3005.
Lock detect (LOCKDET)
This is an active HIGH CMOS output. When active, it
indicates that the transmit PLL is locked to the reference
clock input.
R
Parallel outputs (RXPD0 to RXPD7)
This is a 19.44, 38.88, 77.76 or 155.52 Mbytes/s parallel
CMOS data bus aligned to the parallel output clock
(RXPCLK). RXPD7 is the most significant bit
(corresponding to bit 1 of each PCM word, the first bit
received). RXPD0 is the least significant bit
(corresponding to bit 8 of each PCM word, the last bit
received). RXPD0 to RXPD7 are updated on the falling
RANSMITTER OUTPUT SIGNALS
ECEIVER OUTPUT SIGNALS
Objective specification
TZA3005