tza3005 NXP Semiconductors, tza3005 Datasheet - Page 18

• Manufacturer Part Number: tza3005
• Description: Sdh/sonet Stm1/oc3 And Stm4/oc12 Transceiver
• Manufacturer: NXP Semiconductors

Philips Semiconductors
APPLICATION INFORMATION
It is sometimes necessary to ‘forward clock’ data in an
SDH/SONET system. When this is the case, the parallel
data clock and the reference clock from which the high
speed serial clock is synthesized will both originate from
the same (usually TTL/CMOS) clock source. The following
sections explain how to configure the TZA3005 to
operated in this mode.
Clock control logic description
The timing control logic in the TZA3005 automatically
generates an internal load signal with a fixed relationship
to the reference clock. The logic takes into account the
variation between the reference clock and the internal load
signal over temperature and voltage.
1997 Aug 05
handbook, full pagewidth
SDH/SONET STM1/OC3 and
STM4/OC12 transceiver
TXPCLK
TXPD0 to
TXPD7
handbook, halfpage
Fig.10 TZA3005 with data clocked by reference clock.
Fig.11 Data timing with respect to reference clock.
ASIC
propagation delay <3.5 ns
8
CONVERTER
TTL/PECL
data
18
The connections required to implement the design are
shown in Fig.10, and the timing specifications are shown
in Fig.11. The specified set-up and hold times must be met
by the controller ASIC. It is recommended to latch the data
on the falling edge of the reference clock in order to satisfy
the appropriate specifications.
PECL output termination
The PECL outputs have to be terminated with
50
Thevenin termination can be used as shown in Fig.11.
Reference clock
Reference clock jitter must be minimized to ensure
SONET jitter generation specifications are met. It may
prove difficult to meet these specifications if a TTL source
is used for the reference clock.
PECL
TXPCLK
TXPD0 to TXPD7
to VCC
TZA3005
2
REFCLK
t su
MGK492
t h
2.0V. If this voltage is not available, a
serial
data
Objective specification
MGK493
TZA3005