tza3005 NXP Semiconductors, tza3005 Datasheet - Page 7

• Manufacturer Part Number: tza3005
• Description: Sdh/sonet Stm1/oc3 And Stm4/oc12 Transceiver
• Manufacturer: NXP Semiconductors

Philips Semiconductors
FUNCTIONAL DESCRIPTION
Introduction
The TZA3005 transceiver implements SDH/SONET
serialization/deserialization, transmission and frame
detection/recovery functions. The block diagram in Fig.1
illustrates the basic operation of the chip. The TZA3005
can be used to implement the front-end of SONET
equipment, which consists primarily of the serial transmit
and receive interfaces. The chip handles all the functions
of these two elements, including parallel-to-serial and
serial-to-parallel conversion, clock generation, and system
timing. The system timing circuitry handles data stream
management, framing, and clock distribution throughout
the front-end.
The TZA3005 is divided into a transmitter section and a
receiver section. The sequence of operations is as follows:
Internal clocking and control functions are transparent to
the user. Details of data timing can be found in Figs 3 to 9.
Table 2 Suggested interface devices
1997 Aug 05
Philips
PMC-Sierra
Transmitter operations:
– 4- or 8-bit parallel input
– Parallel-to-serial conversion
– Serial output
Receiver operations:
– Serial input
– Frame detection
– Serial-to-parallel conversion
– 4- or 8-bit parallel output.
SDH/SONET STM1/OC3 and
STM4/OC12 transceiver
MANUFACTURER
TZA3004
TZA3000
TZA3001
SA5225
SA5223
PM5312
PM5355
TYPE
DATA RATE
622 or 155
155 or 622
(Mbits/s)
622
622
155
155
622
7
Transmitter operation
The TZA3005 transceiver chip performs the serializing
stage in the processing of a transmit STM1/OC3 or
STM4/OC12 serial bitstream. It converts the byte
serial 19.44, 38.88 or 77.76 Mbytes/s data stream to bit
serial format at 155.52 or 622.08 Mbits/s. Diagnostic
loopback is provided (transmitter to receiver). Line
loopback is also provided (receiver to transmitter).
An integral frequency synthesizer, consisting of a
phase-locked loop with a divider in the loop, can be used
to generate a high-frequency bit clock from a 19.44, 38.88,
51.84 or 77.76 MHz reference frequency.
C
The serial output clock is generated by the clock
synthesizer (see Fig.1). This signal is phase synchronized
with the input reference clock (REFCLK). Two output clock
frequencies are available, synthesized from any of four
SDH/SONET reference frequencies.
The MODE input is used to select the serial output clock
frequency: 622.08 MHz for STM4/OC12 or 155.52 MHz
for STM1/OC3 (see Table 1).
Table 1 Clock frequency options
clock recovery
optical receiver
laser driver
limiting amplifier
transimpedance amplifier
transport terminal transceiver
Saturn user network interface
LOCK SYNTHESIZER
MODE
1
0
OUTPUT CLOCK
FREQUENCY
622.08 MHz
155.52 MHz
FUNCTION
Objective specification
OPERATING MODE
STM4/OC12
STM1/OC3
TZA3005