r2j20656anp Renesas Electronics Corporation., r2j20656anp Datasheet
r2j20656anp
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r2j20656anp Summary of contents
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... Integrated Driver - MOS FET (DrMOS) Description The R2J20656ANP multi-chip module incorporates a high-side MOS FET, low-side MOS FET, and MOS-FET driver in a single QFN package. The on and off timing of the power MOS FET is optimized by the built-in driver, making this device suitable for large-current buck converters. The chip also incorporates a high-side bootstrap switch, eliminating the need for an external SBD for this purpose ...
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... R2J20656ANP Block Diagram THWN THWN THDN DISBL# 2 μA CGND CGND VCIN Zero 160 k Current Det. ZCD_EN# VCIN Input Logic PWM (TTL Level) (3 state in) CGND Notes: 1. Truth table for the DISBL# pin DISBL# Input Driver Chip Status "L" Shutdown (GL "L") " ...
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... R2J20656ANP Pin Arrangement VIN VIN VIN VIN VSWH PGND PGND PGND PGND PGND Note: All die-pads (three pads in total) should be soldered to PCB. Pin Description Pin Name Pin No. ZCD_EN# 1 VCIN 2 VDRV 3 BOOT 4 CGND 5, 37, Pad GH 6 VIN 8 to 14, Pad VSWH 7, 15 35, Pad ...
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... R2J20656ANP Absolute Maximum Ratings Item Power dissipation Average output current Input voltage Supply voltage & Drive voltage Switch node voltage BOOT voltage I/O voltage THWN/THDN current Operating junction temperature Storage temperature Notes: 1. Pt(25) represents a PCB temperature of 25°C, and Pt(110) represents 110C. ...
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... R2J20656ANP Recommended Operating Condition Item Input voltage Supply voltage & Drive voltage Electrical Characteristics Item Supply VCIN start threshold VCIN shutdown threshold UVLO hysteresis VCIN operating current VCIN disable current PWM PWM input high level input PWM input low level PWM input resistance ...
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... R2J20656ANP Typical Application 4 PWM1 PWM PWM2 Control PWM3 Circuit PWM4 R07DS0201EJ0100 Rev.1.00 Jan 25, 2011 VCIN VDRV BOOT GH THWN VIN R2J20656 DISBL# VSWH ANP ZCD_EN# PGND PWM CGND GL VCIN VDRV BOOT GH THWN VIN R2J20656 DISBL# VSWH ANP ZCD_EN# PGND PWM ...
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... Power GND Signal GND R07DS0201EJ0100 Rev.1.00 Jan 25, 2011 +5 V 0.1 μ VIN CGND PAD PAD 13 14 VIN 15 VSWH R2J20656ANP 16 PGND 17 VSWH PAD Preliminary 1.0 μF CGND ZCD_EN#able Signal INPUT CGND 2 1 PWM 40 PWM INPUT DISBL# 39 THWN 38 10 kΩ ...
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... OUT O O Efficiency = OUT IN P (DrMOS – P LOSS 27°C R07DS0201EJ0100 Rev.1.00 Jan 25, 2011 V VCIN BOOT DISBL# VIN R2J20656ANP VDRV VSWH ZCD_EN# PWM PGND CGND GH GL CIN OUT Preliminary Electric I O load Average Output Voltage Averaging V V circuit ...
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... R2J20656ANP Typical Data Power Loss vs. Output Current 9 VIN = VCIN = VDRV = 5 V VOUT = 1 600 kHz 7 PWM L = 0.45 μ Output Current (A) Power Loss vs. Output Voltage 1.7 VIN = 12 V 1.6 VCIN = VDRV = 600 kHz PWM L = 0.45 μH 1.5 IOUT = 25 A 1.4 1.3 1.2 1.1 1.0 0.9 0.8 0.8 1.2 1.6 2.0 2.4 2.8 3.2 3.6 4.0 4.4 Output Voltage (V) R07DS0201EJ0100 Rev ...
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... R2J20656ANP Power Loss vs. Output Inductance 1.7 VIN = 12 V 1.6 VCIN = VDRV = 5 V VOUT = 1 600 kHz PWM IOUT = 25 A 1.4 1.3 1.2 1.1 1.0 0.9 0.8 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 Output Inductance (μH) Average ICIN vs. Switching Frequency 70 VIN = 12 V VCIN = VDRV = VOUT = 1 0.45 μH IOUT = 250 500 750 Switching Frequency (kHz) R07DS0201EJ0100 Rev ...
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... R2J20656ANP Description of Operation The DrMOS multi-chip module incorporates a high-side MOS FET, low-side MOS FET, and MOS-FET driver in a single QFN package. Since the parasitic inductance between each chip is extremely small, the module is highly suitable for use in buck converters to be operated at high frequencies. The control timing between the high-side MOS FET, low- side MOS FET, and driver is optimized so that high efficiency can be obtained at low output-voltage. VCIN & ...
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... R2J20656ANP DEM Operation (ZCD_EN# = "L" in Light load condition PWM GH GL The PWM input is TTL level and has hysteresis. When the signal route from the control IC is high impedance, the tri- state function turns off the high- and low-side MOS FETs. This function operates when the PWM input signal stays in the input hysteresis window for 150 ns (typ ...
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... R2J20656ANP The equivalent circuit for the PWM-pin input is shown in the next figure the ON state during normal operation; after the PWM input signal has stayed in the hysteresis window for 150 ns (typ.) and the tri-state detection signal has been driven high, the transistor M1 is turned off. ...
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... Figure 5.1 THDN Signal to the System Controller MOS FET The MOS FETs incorporated in R2J20656ANP are highly suitable for synchronous-rectification buck conversion. For the high-side MOS FET, the drain is connected to the VIN pin and the source is connected to the VSWH pin. For the low-side MOS FET, the drain is connected to the VSWH pin and the source is connected to the PGND pin. ...
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... JEITA Package Code RENESAS Code P-HVQFN40-p-0606-0.50 PVQN0040KE HD INDEX 1.95 2-A section CAV No. Die No. 1. Ordering Information Part Name R2J20656ANP#G0 R07DS0201EJ0100 Rev.1.00 Jan 25, 2011 Previous Code MASS[Typ.] — — 4-C0.50 1pin Quantity 2500 pcs Preliminary ...
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... Unit 906, Block B, Menara Amcorp, Amcorp Trade Centre, No. 18, Jln Persiaran Barat, 46050 Petaling Jaya, Selangor Darul Ehsan, Malaysia Tel: +60-3-7955-9390, Fax: +60-3-7955-9510 Renesas Electronics Korea Co., Ltd. 11F., Samik Lavied' or Bldg., 720-2 Yeoksam-Dong, Kangnam-Ku, Seoul 135-080, Korea Tel: +82-2-558-3737, Fax: +82-2-558-5141 Notice © 2011 Renesas Electronics Corporation. All rights reserved. http://www.renesas.com Colophon 1.0 ...