r2j20656anp Renesas Electronics Corporation., r2j20656anp Datasheet - Page 2
![no-image](/images/manufacturer_photos/0/5/561/renesas_electronics_corporation__sml.jpg)
r2j20656anp
Manufacturer Part Number
r2j20656anp
Description
Integrated Driver - Mos Fet Drmos
Manufacturer
Renesas Electronics Corporation.
Datasheet
1.R2J20656ANP.pdf
(16 pages)
R2J20656ANP
Block Diagram
ZCD_EN#
Notes: 1. Truth table for the DISBL# pin
R07DS0201EJ0100 Rev.1.00
Jan 25, 2011
DISBL#
THWN
PWM
3. Output signal from the UVL block
5. Truth table for the THDN block
"L"
"Open"
"H"
< 150°C
> 150°C
UVL output
Logic Level
DISBL# Input
Driver IC Temp.
CGND
VCIN
Input Logic
(TTL Level)
(3 state in)
CGND
160 k
VCIN
THWN
CGND
2 μA
"H"
"L"
Zero
Current
Det.
For shutdown
Shutdown (GL, GH = "L")
Shutdown (GL, GH = "L")
Enable (GL, GH = "Active")
THDN
Enable (GL, GH = "Active")
Shutdown (GL, GH = "L")
(latch-off)
Driver Chip Status
Driver Chip Status
VL
VCIN
UVL
VH
For active
Level Shifter
VDRV
VCIN
Overlap
Protection.
& Logic
Boot
SW
BOOT
VDRV
35 k
2. Truth table for the ZCD_EN# pin
4. Output signal from the THWN block
"L"
"Open"
"H"
ZCD_EN# Input
Thermal Warning
Logic Level
GH
20 k
GL
Driver Chip
"H"
"L"
"Diode Emulation Mode"
"Continuous Conduction
Mode"
"Continuous Conduction
Mode"
Normal
operating
Driver Chip Status
TwarnL
TwarnH
VIN
VSWH
PGND
Preliminary
Page 2 of 15
Thermal
Warning
High Side
MOS FET
Low Side
MOS FET
T
IC
(°C)