l99mc6tr-lf STMicroelectronics, l99mc6tr-lf Datasheet - Page 29

• Manufacturer Part Number: l99mc6tr-lf
• Description: Configurable 6-channel Device
• Manufacturer: STMicroelectronics

L99MC6
8.2
8.2.1
8.2.2
SPI communication flow
General description
The proposed SPI communication is based on a standard SPI interface structure using CSN
(chip select not), SDI (serial data in), SDO (serial data out/error) and SCK (serial clock)
signal lines.
At the beginning of each communication the master reads the <SPI-frame-ID> register
(ROM address 3EH) of the slave device. This 8-bit register indicates the SPI frame length
(16 bit for the L99MC6) and the availability of additional features.
Each communication frame consists of an instruction byte which is followed by 1 data byte
(see
The data returned on SDO within the same frame always starts with the <Global Status>
register. It provides general status information about the device. It is followed by 1 byte (that
is ‘In-frame-response’, see
For Write cycles the <Global Status> register is followed by the previous content of the
addressed register.
For Read cycles the <Global Status> register is followed by the content of the addressed
register.
Table 12.
Table 13.
Command byte
Each communication frame starts with a command byte. It consists of an operating code
which specifies the type of operation (<Read>, <Write>, <Read and Clear Status>, <Read
Device Information>) and a 6-bit address.
Table 14.
MSB
MSB
Figure
OC1
MSB
OC1
Bit7
Operating code
Operating code
12).
Command byte - general description
Data byte - general description
Command byte
Bit6
OC0
OC0
Figure
Bit5
Doc ID 16523 Rev 1
A5
A5
12).
Bi4
A4
A4
Bit3
A3
A3
Address
Address
Functional description of the SPI
Bit2
A2
A2
Bit1
A1
A1
LSB
LSB
Bit0
LSB
A0
A0
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