l99mc6tr-lf STMicroelectronics, l99mc6tr-lf Datasheet - Page 32

• Manufacturer Part Number: l99mc6tr-lf
• Description: Configurable 6-channel Device
• Manufacturer: STMicroelectronics

Functional description of the SPI
Note:
8.3
Note:
8.4
32/55
For Read operations, the <communication error> bit in the <Global Status Register> is set,
but the register to be read is still transferred to the DO pin. If the number of clock cycles is
smaller than the frame width, the data at DO is truncated. If the number of clock cycles is
larger than the frame width, the data at DO is filled with ‘0’ bits.
Due to this safety functionality a daisy chaining of SPI is not possible. Instead, a parallel
operation of the SPI bus by controlling the CSN signal of the connected ICs is
recommended.
If the frame width is greater than 16 bits, initial Read of <SPI-frame-ID> using a 16-bit
communication sets the <communication Error bit> of the <Global Status> register. A
subsequent correct length transaction is necessary to correct this bit.
Write operation
OC0, OC1: operating code (00 for ‘Write’ mode)
Table 18.
The Write operation starts with a command byte followed by 1 data byte.
For Write cycles the <Global Status> register is followed by the previous content of the
addressed register.
The RAM memory area consists of 8-bit registers. All unused RAM addresses are read as
‘0’.
Failures are indicated by activating the corresponding bit of the <Global Status> register.
The register definition for RAM address 00H is device specific.
A register value of all 0 causes a device reset (interpreted as ‘Data-in short to GND’).
Read operation
OC0, OC1: operating code (01 for ‘Read’ mode)
Table 19.
The Read operation starts with a command byte followed by 1 data byte. The content of the
data byte is ‘do not care’. The content of the addressed register is shifted out at SDO within
the same frame (‘in-frame response’).
The returned data byte represents the content of the register to be read.
Failures are indicated by activating the corresponding bit of the <Global Status> register.
MSB
MSB
Operating code
Operating code
0
0
Command byte for Write mode
Command byte for Read mode
0
1
Doc ID 16523 Rev 1
A5
A5
A4
A4
A3
A3
Address
Address
A2
A2
A1
A1
L99MC6
LSB
LSB
A0
A0