W134 Cypress Semiconductor Corp., W134 Datasheet - Page 2

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W134

Manufacturer Part Number
W134
Description
400 MHZ DRCG
Manufacturer
Cypress Semiconductor Corp.
Datasheet

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Pin Definitions
Document #: 38-07426 Rev. **
REFCLK
PCLKM
SYNCLKN
STOPB
PWRDNB
MULT 0:1
CLK, CLKB
S0, S1
NC
VDDIR
VDDIPD
VDD
GND
Pin Name
3, 9, 16, 22
4, 5, 8, 13,
15, 14
20, 18
24, 23
17, 21
Pin
No.
11
12
19
10
2
6
7
1
Type
RefV
RefV
Pin
O
P
G
I
I
I
I
I
I
I
-
Reference Clock Input: Reference clock input, normally supplied by a system
frequency synthesizer (Cypress W133).
Phase Detector Input: The phase difference between this signal and SYNCLKN
is used to synchronize the Rambus Channel Clock with the system clock. Both
PCLKM and SYNCLKN are provided by the Gear Ratio Logic in the memory con-
troller. If Gear Ratio Logic is not used, this pin would be connected to Ground.
Phase Detector Input: The phase difference between this signal and PCLKM is
used to synchronize the Rambus Channel Clock with the system clock. Both
PCLKM and SYNCLKN are provided by the Gear Ratio Logic in the memory con-
troller. If Gear Ratio Logic is not used, this pin would be connected to Ground.
Clock Output Enable: When this input is driven to active LOW, it disables the
differential Rambus Channel clocks.
Active LOW Power-Down: When this input is driven to active LOW, it disables the
differential Rambus Channel clocks and places the W134M/W134S in power-down
mode.
PLL Multiplier Select: These inputs select the PLL prescaler and feedback divid-
ers to determine the multiply ratio for the PLL for the input REFCLK.
Complementary Output Clock: Differential Rambus Channel clock outputs.
Mode Control Input: These inputs control the operating mode of the
W134M/W134S.
No Connect
Reference for REFCLK: Voltage reference for input reference clock.
Reference for Phase Detector: Voltage reference for phase detector inputs and
StopB.
Power Connection: Power supply for core logic and output buffers. Connected to
3.3V supply.
Ground Connection: Connect all ground pins to the common system ground
plane.
MULT0
0
0
1
1
S0
0
0
1
1
MULT1
0
1
1
0
Pin Description
S1
0
1
0
1
PLL/REFCLK
W134M
5.333
4.5
6
8
Output Enable Test
Normal
Bypass
MODE
Test
W134M/W134S
PLL/REFCLK
W134S
5.333
4
6
8
Page 2 of 13

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