W134 Cypress Semiconductor Corp., W134 Datasheet - Page 5

• Manufacturer Part Number: W134
• Description: 400 MHZ DRCG
• Manufacturer: Cypress Semiconductor Corp.

Table 3. Clock Stop Mode Selection
Table 4 shows the logic for selecting the Bypass and Test
modes. The select bits, S0 and S1, control the selection of
these modes. The Bypass mode brings out the full-speed PLL
output clock, bypassing the Phase Aligner. The Test mode
brings the Refclk input all the way to the output, bypassing both
the PLL and the Phase Aligner. In the Output Test mode (OE),
both the Clk and ClkB outputs are put into a high-impedance
state (Hi-Z). This can be used for component testing and for
board-level testing.
Table 4. Bypass and Test Mode Selection
Table 5 shows the logic for selecting the Power-down mode,
using the PwrDnB input signal. PwrDnB is active LOW (en-
abled when 0). When PwrDnB is disabled, the DRCG is in its
normal mode. When PwrDnB is enabled, the DRCG is put into
a powered-off state, and the Clk and ClkB outputs are three-
stated.
Table 6. Examples of Frequencies, Dividers, and Gear Ratios
Document #: 38-07426 Rev. **
Normal
Output Test (OE)
Bypass
Test
Clk Stop
Normal
Mode
Pclk
100
100
133
133
Mode
67
StopB
Refclk
1
0
S0
V
0
0
1
1
33
50
50
67
67
DD
Turn-On
S1
0
1
0
1
V
DD
Test
Bypclk
PLLclk
V
Refclk
Busclk
M
(int.)
Turn-On
PAclk
Gnd
X,STOP
267
300
400
267
400
Clk
K
-
Power-Down
PLLclk PLLclkB
Refclk
Figure 4. Clock Source State Diagram
PAclk
Hi-Z
Clk
N
L
Synclk
B
V
PAclkB
100
100
ClkB
X,STOP
67
75
67
RefclkB
PAclkB
ClkB
Hi-Z
A
V
DD
Normal
A
8
6
8
4
6
Turn-On
G
Table 5. Power-down Mode Selection
Table of Frequencies and Gear Ratios
Table 6 shows several supported Pclk and Busclk frequencies,
the corresponding A and B dividers required in the DRCG PLL,
and the corresponding M and N dividers in the gear ratio logic.
The column Ratio gives the Gear Ratio as defined Pclk/Synclk
(same as M and N). The column F@PD gives the divided down
frequency
F@PD = Pclk/M = Synclk/N.
State Transitions
The clock source has three fundamental operating states. Fig-
ure 4 shows the state diagram with each transition labelled A
through H. Note that the clock source output may NOT be
glitch-free during state transitions.
Upon powering up the device, the device can enter any state,
depending on the settings of the control signals, PwrDnB and
StopB.
In Power-down mode, the clock source is powered down with
the control signal, PwrDnB, equal to 0. The control signals S0
and S1 must be stable before power is applied to the device,
and can only be changed in Power-down mode (PwrDnB = 0).
The reference inputs, V
be grounded during the Power-down mode.
D
C
Power-down
Normal
Mode
E
B
1
1
1
1
1
J
(in
Clk Stop
F
MHz)
PwrDnB
M
2
8
4
4
8
1
0
DDR
at the Phase Detector,
and V
N
2
6
4
2
6
V
DDPD
DD
H
PAclk
GND
Clk
W134M/W134S
, may remain on or may
Turn-On
Ratio
1.33
1.33
1.0
1.0
2.0
Page 5 of 13
PAclkB
ClkB
GND
F@PD
12.5
16.7
33
25
33
where