W134 Cypress Semiconductor Corp., W134 Datasheet - Page 7

• Manufacturer Part Number: W134
• Description: 400 MHZ DRCG
• Manufacturer: Cypress Semiconductor Corp.

Table 8. State Transition Latency Specifications
Figure 5 shows that the Clk Stop to Normal transition goes
through three phases. During t
specified and can have glitches. For t
clock output is enabled and must be glitch-free. For
t > t
Document #: 38-07426 Rev. **
Transition
CLKSETL
B,D
M
C
G
H
N
A
K
E
E
F
J
L
, the clock output phase must be settled to within
Normal or Clk Stop
Power-down
Power-down
Power-down
Clk Stop
Clk Stop
V
V
V
Normal
Normal
Normal
From
DD
DD
DD
Test
ON
ON
ON
CLKON
Power-down
CLKON
, the clock output is not
Clk Stop
Clk Stop
Clk Stop
Normal
Normal
Normal
Normal
Normal
Normal
Test
Test
Test
To
< t < t
CLKSETL
t
t
t
t
t
t
t
POWERUP
POWERUP
POWERUP
POWERUP
POWERUP
POWERUP
t
POWERDN
Symbol
Transition Latency
t
CLKSETL
t
CLKOFF
t
CLKON
MULT
t
t
, the
CTL
CTL
50 ps of the phase before the clock output was disabled. At this
time, the clock output must also meet the voltage and timing
specifications of Table 14. The outputs are in a high-imped-
ance state during the Clk Stop mode.
20 cycles
10 ns
Max.
3 ms
3 ms
3 ms
3 ms
3 ms
3 ms
1 ms
3 ms
3 ms
1 ms
5 ns
Time from PwrDnB to Clk/ClkB output settled
(excluding t
Time from PwrDnB until the internal PLL and
clock has turned ON and settled.
Time from PwrDnB to Clk/ClkB output settled
(excluding t
Time from V
Clk/ClkB output settled (excluding t
Time from V
internal PLL and clock has turned ON and
settled.
Time from V
internal PLL and clock has turned ON and
settled.
Time from when Mult0 or Mult1 changed until
Clk/ClkB output resettled (excluding
t
Time from StopB until Clk/ClkB provides
glitch-free clock edges.
Time from StopB to Clk/ClkB output settled to
within 50 ps of the phase before CLK/CLKB
was disabled.
Time from StopB
disabled.
Time from when S0 or S1 is changed until
CLK/CLKB output has resettled (excluding
t
Time from when S0 or S1 is changed until
CLK/CLKB output has resettled (excluding
t
Time from PwrDnB
down.
DISTLOCK
DISTLOCK
DISTLOCK
).
).
).
DISTLOCK
DISTLOCK
DD
DD
DD
is applied and settled until
is applied and settled until
is applied and settled until
Description
to Clk/ClkB output
).
).
W134M/W134S
to the device in Power-
Page 7 of 13
DISTLOCK
).