tmp86c408idmg TOSHIBA Semiconductor CORPORATION, tmp86c408idmg Datasheet - Page 20
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tmp86c408idmg
Manufacturer Part Number
tmp86c408idmg
Description
Cmos 8-bit Microcontroller
Manufacturer
TOSHIBA Semiconductor CORPORATION
Datasheet
1.TMP86C408IDMG.pdf
(152 pages)
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2.2 System Clock Controller
2. Operational Description
High-frequency
Low-frequency
2.2.2 Timing Generator
2.2.2.1
clock fc
clock fs
SYSCK
DV7CK
from the basic clock (fc or fs). The timing generator provides the following functions.
The timing generator generates the various system clocks supplied to the CPU core and peripheral hardware
and machine cycle counters.
TBTCR<DV7CK>, that is shown in Figure 2-4. As reset and STOP mode started/canceled, the prescaler
and the divider are cleared to “0”.
1. Generation of main system clock
2. Generation of divider output (
3. Generation of source clocks for time base timer
4. Generation of source clocks for watchdog timer
5. Generation of internal source clocks for timer/counters
6. Generation of warm-up clocks for releasing STOP mode
Configuration of timing generator
The timing generator consists of a 2-stage prescaler, a 21-stage divider, a main system clock generator,
An input clock to the 7th stage of the divider depends on the operating mode, SYSCR2<SYSCK> and
Timer counter, Serial interface, Time-base-timer, divider output, etc. (Peripheral functions)
1
2
fc/4
Main system clock generator
Figure 2-4 Configuration of Timing Generator
1
2
3
4
5 6
DVO
plexer
Multi-
A
B
) pulses
S
Page 10
Y
7
fc or fs
8
9
10
11
12
13
Divider
14
Machine cycle counters
15
16
17 18 19 20 21
B0
B1
A0 Y0
A1 Y1
TMP86C408IDMG
S
Multiplexer
Warm-up
controller
Watchdog
timer
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