tmp86c408idmg TOSHIBA Semiconductor CORPORATION, tmp86c408idmg Datasheet - Page 7

• Manufacturer Part Number: tmp86c408idmg
• Description: Cmos 8-bit Microcontroller
• Manufacturer: TOSHIBA Semiconductor CORPORATION

9. 8-Bit TimerCounter (TC3, TC4)
10. Asynchronous Serial interface (UART )
11. Serial Expansion Interface (SEI)
9.1
9.2
9.3
10.1
10.2
10.3
10.4
10.5
10.6
10.7
10.8
10.9
11.1
11.2
11.3
11.4
8.3.6
9.3.1
9.3.2
9.3.3
9.3.4
9.3.5
9.3.6
9.3.7
9.3.8
9.3.9
10.8.1
10.8.2
10.9.1
10.9.2
10.9.3
10.9.4
10.9.5
10.9.6
11.2.1
11.2.2
11.2.3
11.3.1
11.3.2
11.4.1
11.4.2
Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
TimerCounter Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
Function. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
9.3.9.1
9.3.9.2
11.2.1.1
Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
Control
Transfer Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
Transfer Rate. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
Data Sampling Method . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
STOP Bit Length . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
Parity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
Transmit/Receive Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
Status Flag . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
SEI Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
SEI Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
SEI Pin Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
Programmable Pulse Generate (PPG) Output Mode ............................................................................. 77
8-Bit Timer Mode (TC3 and 4) ................................................................................................................ 87
8-Bit Event Counter Mode (TC3, 4) ........................................................................................................ 88
8-Bit Programmable Divider Output (PDO) Mode (TC3, 4)..................................................................... 88
8-Bit Pulse Width Modulation (PWM) Output Mode (TC3, 4).................................................................. 91
16-Bit Timer Mode (TC3 and 4) .............................................................................................................. 93
16-Bit Event Counter Mode (TC3 and 4) ................................................................................................ 94
16-Bit Pulse Width Modulation (PWM) Output Mode (TC3 and 4).......................................................... 94
16-Bit Programmable Pulse Generate (PPG) Output Mode (TC3 and 4) ............................................... 97
Warm-Up Counter Mode......................................................................................................................... 99
Data Transmit Operation .................................................................................................................... 106
Data Receive Operation ..................................................................................................................... 106
Parity Error.......................................................................................................................................... 107
Framing Error...................................................................................................................................... 107
Overrun Error ...................................................................................................................................... 107
Receive Data Buffer Full..................................................................................................................... 108
Transmit Data Buffer Empty ............................................................................................................... 108
Transmit End Flag .............................................................................................................................. 109
SEI Control Register (SECR).............................................................................................................. 112
SEI Status Register (SESR) ............................................................................................................... 113
SEI Data Register (SEDR).................................................................................................................. 113
Controlling SEI clock polarity and phase ............................................................................................ 114
SEI data and clock timing ................................................................................................................... 114
SCLK pin............................................................................................................................................. 115
MISO/MOSI pins ................................................................................................................................. 115
Low-Frequency Warm-up Counter Mode
High-Frequency Warm-Up Counter Mode
Transfer rate
(NORMAL1 → NORMAL2 → SLOW2 → SLOW1)
(SLOW1 → SLOW2 → NORMAL2 → NORMAL1)
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
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