tmp86c408idmg TOSHIBA Semiconductor CORPORATION, tmp86c408idmg Datasheet - Page 51

• Manufacturer Part Number: tmp86c408idmg
• Description: Cmos 8-bit Microcontroller
• Manufacturer: TOSHIBA Semiconductor CORPORATION

3.5 Software Interrupt (INTSW)
3.6 Undefined Instruction Interrupt (INTUNDEF)
3.7 Address Trap Interrupt (INTATRAP)
3.8 External Interrupts
3.5.1 Address error detection
3.5.2 Debugging
is highest prioritized interrupt).
erated when the CPU fetches such a code and tries to execute it. INTUNDEF is accepted even if non-maskable inter-
rupt is in process. Contemporary process is broken and INTUNDEF interrupt process starts, soon after it is
requested.
trap interrupt (INTATRAP). INTATRAP is accepted even if non-maskable interrupt is in process. Contemporary pro-
cess is broken and INTATRAP interrupt process starts, soon after it is requested.
(Pulse inputs of less than a certain time are eliminated as noise).
interrupt input pin or an input/output port, and is configured as an input port during reset.
control register (EINTCR).
Executing the SWI instruction generates a software interrupt and immediately starts interrupt processing (INTSW
Use the SWI instruction only for detection of the address error or for debugging.
Taking code which is not defined as authorized instruction for instruction causes INTUNDEF. INTUNDEF is gen-
Note: The undefined instruction interrupt (INTUNDEF) forces CPU to jump into vector address, as software interrupt
Fetching instruction from unauthorized area for instructions (Address trapped area) causes reset output or address
Note: The operating mode under address trapped, whether to be reset output or interrupt processing, is selected on
The TMP86C408IDMG has 5 external interrupt inputs. These inputs are equipped with digital noise reject circuits
Edge selection is also possible with INT1,INT3,INT4. The
Edge selection, noise reject control and
memory address during single chip mode. Code FFH is the SWI instruction, so a software interrupt is gener-
ated and an address error is detected. The address error detection range can be further expanded by writing
FFH to unused areas of the program memory. Address trap reset is generated in case that an instruction is
fetched from RAM or SFR areas.
address.
Note 1: It is recommended that stack pointer be return to rate before INTATRAP (Increment 3 times), if return inter-
Note 2: When the interrupt processing time is longer than the interrupt request generation time, the interrupt service
FFH is read if for some cause such as noise the CPU attempts to fetch an instruction from a non-existent
Debugging efficiency can be increased by placing the SWI instruction at the software break point setting
(SWI) does.
watchdog timer control register (WDTCR).
rupt instruction [RETN] is not utilized during interrupt service program under INTATRAP (such as Example
2).
task is performed but not the main task.
INT0
/P10 pin function selection are performed by the external interrupt
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INT0
/P10 pin can be configured as either an external
TMP86C408IDMG