tmp86c408idmg TOSHIBA Semiconductor CORPORATION, tmp86c408idmg Datasheet - Page 40

• Manufacturer Part Number: tmp86c408idmg
• Description: Cmos 8-bit Microcontroller
• Manufacturer: TOSHIBA Semiconductor CORPORATION

2.3 Reset Circuit
2. Operational Description
Instruction
execution
Internal reset
2.3.2 Address trap reset
2.3.3 Watchdog timer reset
2.3.4 System clock reset
Note 1: Address “a” is on-chip RAM (WDTCR1<ATAS> = “1”) space or SFR area.
Note 2: During reset release, reset vector “r” is read out, and an instruction at address “r” is fetched and decoded.
from the on-chip RAM (when WDTCR1<ATAS> is set to “1”) or SFR area, address trap reset will be gener-
ated. The reset time is maximum 24/fc[s] (1.5µs at 16.0 MHz).
CPU. (The oscillation is continued without stopping.)
If the CPU should start looping for some cause such as noise and an attempt be made to fetch an instruction
Note:The operating mode under address trapped is alternative of reset or interrupt. The address trap area is alter-
Refer to Section “Watchdog Timer”.
If the condition as follows is detected, the system clock reset occurs automatically to prevent dead lock of the
The reset time is maximum 24/fc (1.5 µs at 16.0 MHz).
- In case of clearing SYSCR2<XEN> and SYSCR2<XTEN> simultaneously to “0”.
- In case of clearing SYSCR2<XEN> to “0”, when the SYSCR2<SYSCK> is “0”.
- In case of clearing SYSCR2<XTEN> to “0”, when the SYSCR2<SYSCK> is “1”.
native.
JP a
Address trap is occurred
Figure 2-16 Address Trap Reset
maximum 24/fc [s]
Page 30
4/fc to 12/fc [s]
Reset release
16/fc [s]
TMP86C408IDMG
Instruction at address r