tmp88cs43fg TOSHIBA Semiconductor CORPORATION, tmp88cs43fg Datasheet - Page 24

• Manufacturer Part Number: tmp88cs43fg
• Description: 8 Bit Microcontroller Tlcs-870/x Series
• Manufacturer: TOSHIBA Semiconductor CORPORATION

2. Functional Description
2.1 Functions of the CPU Core
2.1.4.3
Table 2-1 Single Clock Mode
system clock. The System Control Registers (SYSCR1, SYSCR2) are used to control operation modes of
this circuit. Figure 2-6 shows an operation mode transition diagram, followed by description of the Sys-
tem Control Registers.
Standby Control Circuit
(1)
The Standby Control Circuit starts/stops the high-frequency clock oscillator circuit and selects the main
Single
Clock
mode
IDLE
Operation Mode
ated from the high-frequency clock, the machine cycle time in single clock mode is 4/fc [s].
Single clock mode
Only the high-frequency clock oscillator circuit is used. Because the main system clock is gener-
RESET
NORMAL
IDLE
STOP
1. NORMAL mode
2. IDLE mode
3. STOP mode
Figure 2-6 Operation Mode Transition Diagram
quency clock. The TMP88CS43FG enters this NORMAL mode after reset.
units are operated with the high-frequency clock. IDLE mode is entered into by using System
Control Register 2. The device is placed out of this mode and back into NORMAL mode by
an interrupt from the peripheral hardware or an external interrupt. When IMF (interrupt mas-
ter enable flag) = 1 (interrupt enabled), the device returns to normal operation after the inter-
rupt has been serviced. When IMF = 0 (interrupt disabled), the device restarts execution
beginning with the instruction next to one that placed it in IDLE mode.
state immediately before being stopped, with a minimal amount of power consumed.
input (level or edge selectable). After an elapse of the warm-up time, the device restarts exe-
cution beginning with the instruction next to one that placed it in STOP mode.
In this mode, the CPU core and peripheral hardware units are operated with the high-fre-
In this mode, the CPU and watchdog timer are turned off while the peripheral hardware
The entire system operation including the oscillator circuit is halted, retaining the internal
STOP mode is entered into by using System Control Register 1, and is exited by
Instruction
Interrupt
Frequency
Oscillate
High
Stop
Oscillator Circuit
Frequency
Low
-
NORMAL
Page 14
RESET
mode
Reset deasserted
CPU Core
Operate
Reset
Stop
Input for releasing mode
Instruction
Peripheral
Operate
Circuit
Reset
Stop
Machine Cycle
4/fc [s]
Time
STOP
mode
-
TMP88CS43FG
STOP
pin