tmp89fm42l TOSHIBA Semiconductor CORPORATION, tmp89fm42l Datasheet - Page 11

• Manufacturer Part Number: tmp89fm42l
• Description: 8 Bit Microcontroller Tlcs-870/c1 Series
• Manufacturer: TOSHIBA Semiconductor CORPORATION

19. Key-on Wakeup (KWU)
20. 10-bit AD Converter (ADC)
21. Flash Memory
18.5 Data Transfer of I2C Bus.....................................................................................................290
18.6 AC Specifications................................................................................................................297
18.7 Revision History..................................................................................................................299
19.1 Configuration.......................................................................................................................301
19.2 Control.................................................................................................................................302
19.3 Functions..............................................................................................................................303
20.1 Configuration.......................................................................................................................305
20.2 Control.................................................................................................................................306
20.3
20.4
20.5 Starting STOP/IDLE0/SLOW Modes.................................................................................312
20.6 Analog Input Voltage and AD Conversion Result..............................................................313
20.7 Precautions about the AD Converter...................................................................................314
20.8 Revision History..................................................................................................................315
21.1 Flash Memory Control.........................................................................................................318
21.2 Functions..............................................................................................................................321
18.4.4
18.4.5
18.4.6
18.4.7
18.4.8
18.4.9
18.4.10
18.4.11
18.4.12
18.4.13
18.4.14
18.4.15
18.5.1
18.5.2
18.5.3
18.5.4
18.5.5
20.3.1
20.3.2
20.3.3
20.7.1
20.7.2
20.7.3
21.2.1
21.2.2
21.2.3
18.4.4.1
18.4.4.2
18.5.3.1
18.5.3.2
Functions.............................................................................................................................310
Register Setting...................................................................................................................312
Serial clock....................................................................................................................................................................282
Master/slave selection....................................................................................................................................................284
Transmitter/receiver selection........................................................................................................................................284
Start/stop condition generation......................................................................................................................................284
Interrupt service request and release..............................................................................................................................285
Setting of serial bus interface mode...............................................................................................................................286
Device initialization.......................................................................................................................................................290
Start condition and slave address generation.................................................................................................................290
1-word data transfer.......................................................................................................................................................291
Stop condition generation..............................................................................................................................................294
Restart............................................................................................................................................................................295
Single mode...................................................................................................................................................................310
Repeat mode..................................................................................................................................................................310
AD operation disable and forced stop of AD operation................................................................................................311
Analog input pin voltage range......................................................................................................................................314
Analog input pins used as input/output ports.................................................................................................................314
Noise countermeasure....................................................................................................................................................314
Flash memory command sequence execution and toggle control (FLSCR1 <FLSMD>).............................................321
Flash memory area switching (FLSCR1<FAREA>).....................................................................................................322
RAM area switching (SYSCR3<RAREA>)..................................................................................................................324
Software reset..............................................................................................................................................................286
Arbitration lost detection monitor................................................................................................................................286
Slave address match detection monitor.......................................................................................................................288
GENERAL CALL detection monitor..........................................................................................................................288
Last received bit monitor.............................................................................................................................................289
Slave address and address recognition mode specification.........................................................................................289
Clock source
Clock synchronization
When SBI0SR2<MST> is "1" (Master mode)
When SBI0SR2<MST> is "0" (Slave mode)
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