tmp89fh40 TOSHIBA Semiconductor CORPORATION, tmp89fh40 Datasheet - Page 11

• Manufacturer Part Number: tmp89fh40
• Description: 8 Bit Microcontroller Tlcs-870/c1 Series
• Manufacturer: TOSHIBA Semiconductor CORPORATION

19. Key-on Wakeup (KWU)
20. 10-bit AD Converter (ADC)
21. Flash Memory
18.5 Data Transfer of I2C Bus.....................................................................................................288
18.6 AC Specifications................................................................................................................295
18.7 Revision History..................................................................................................................297
19.1 Configuration.......................................................................................................................299
19.2 Control.................................................................................................................................300
19.3 Functions..............................................................................................................................301
20.1 Configuration.......................................................................................................................303
20.2 Control.................................................................................................................................304
20.3
20.4
20.5 Starting STOP/IDLE0/SLOW Modes.................................................................................310
20.6 Analog Input Voltage and AD Conversion Result..............................................................311
20.7 Precautions about the AD Converter...................................................................................312
21.1 Flash Memory Control.........................................................................................................314
21.2 Functions..............................................................................................................................317
21.3 Command Sequence............................................................................................................324
18.4.7
18.4.8
18.4.9
18.4.10
18.4.11
18.4.12
18.4.13
18.4.14
18.4.15
18.5.1
18.5.2
18.5.3
18.5.4
18.5.5
20.3.1
20.3.2
20.3.3
20.7.1
20.7.2
20.7.3
21.2.1
21.2.2
21.2.3
21.2.4
21.2.5
21.2.6
21.3.1
21.3.2
18.5.3.1
18.5.3.2
Functions.............................................................................................................................308
Register Setting...................................................................................................................310
Start/stop condition generation......................................................................................................................................282
Interrupt service request and release..............................................................................................................................283
Setting of serial bus interface mode...............................................................................................................................284
Device initialization.......................................................................................................................................................288
Start condition and slave address generation.................................................................................................................288
1-word data transfer.......................................................................................................................................................289
Stop condition generation..............................................................................................................................................292
Restart............................................................................................................................................................................293
Single mode...................................................................................................................................................................308
Repeat mode..................................................................................................................................................................308
AD operation disable and forced stop of AD operation................................................................................................309
Analog input pin voltage range......................................................................................................................................312
Analog input pins used as input/output ports.................................................................................................................312
Noise countermeasure....................................................................................................................................................312
Flash memory command sequence execution and toggle control (FLSCR1 <FLSMD>).............................................317
Flash memory area switching (FLSCR1<FAREA>).....................................................................................................318
RAM area switching (SYSCR3<RAREA>)..................................................................................................................320
BOOTROM area switching (FLSCR1<BAREA>).......................................................................................................320
Flash memory standby control (FLSSTB<FSTB>).......................................................................................................322
Port input control register (SPCR<PIN0, PIN1>).........................................................................................................323
Byte program.................................................................................................................................................................324
Sector erase (4-kbyte partial erase)................................................................................................................................325
Software reset..............................................................................................................................................................284
Arbitration lost detection monitor................................................................................................................................284
Slave address match detection monitor.......................................................................................................................286
GENERAL CALL detection monitor..........................................................................................................................286
Last received bit monitor.............................................................................................................................................287
Slave address and address recognition mode specification.........................................................................................287
When SBI0SR2<MST> is "1" (Master mode)
When SBI0SR2<MST> is "0" (Slave mode)
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