tmp19a43fd TOSHIBA Semiconductor CORPORATION, tmp19a43fd Datasheet - Page 54

• Manufacturer Part Number: tmp19a43fd
• Description: 32-bit Risc Microprocessor
• Manufacturer: TOSHIBA Semiconductor CORPORATION

Note:
8) Automatic erasing of protection bits
because the protection bits may not have been correctly programmed. If all the protection bits have
been programmed, the flash memory cannot be read from any area outside the flash memory such
as the internal RAM. In this condition, the FLCS <BLPRO 3:0> bits are set to "0 x F" indicating
that it is in the protected state (See Table 24.6). After this, no command writing can be performed.
Different results will be obtained when the automatic protection bit erase command is executed
depending on the status of the protection bits. It depends on the status of FLCS <BLPRO 3:0>
before the command execution whether it is set to "0 x F" or to any other values. Be sure to check
the value of FLCS <BLPRO 3:0> before executing the automatic protection bit erase command.
x
x
In any case, any new command sequence is not accepted while it is in an automatic operation to
erase protection bits. If it is desired to stop the operation, use the hardware reset function. When
the automatic operation to erase protection bits is normally terminated, it returns to the read mode.
The FLCS <RDY/BSY> bit is "0" while in automatic operation and it turns to "1"
when the automatic operation is terminated.
When FLCS <BLPRO 3:0> is set to "0 x F" (all the protection bits are programmed):
When FLCS <BLPRO 3:0> is other than "0 x F" (not all the protection bits are
When the automatic protection bit erase command is command written, the flash memory is
automatically initialized within the device. When the seventh bus write cycle is completed, the
entire area of the flash memory data cells is erased and then the protection bits are erased.
This operation can be checked by monitoring FLCS <RDY/BSY>. If the automatic operation
to erase protection bits is normally terminated, FLCS will be set to "0x01." While no
automatic verify operation is performed internally to the device, be sure to read the data to
confirm that it has been correctly erased. For returning to the read mode while the automatic
operation after the seventh bus cycle is in progress, it is necessary to use the hardware reset to
reset the flash memory or the device. If this is done, it is necessary to check the status of
protection bits by FLCS <BLPRO 3:0> after retuning to the read mode and perform either the
automatic protection bit erase, automatic chip erase, or automatic block erase operation, as
appropriate.
programmed):
The protection condition can be canceled by the automatic protection bit erase operation. With
this device, protection bits can be erased handling two bits at a time. The target bits are
specified in the seventh bus write cycle and when the command is completed, the device is in
a condition the two bits are erased. The protection status of each block can be checked by
FLCS <BLPRO 3:0> to be described later. This status of the programming operation for
automatic protection bits can be checked by monitoring FLCS <RDY/BSY>. When the
automatic operation to erase protection bits is normally terminated, the two protection bits of
FLCS <BLPRO 3:0> selected for erasure are set to "0."
Software reset is ineffective in the seventh bus write cycle of the automatic
protection bit programming command. The FLCS <RDY/BSY> bit turns to "0"
after entering the seventh bus write cycle.
TMP19A43 (rev2.0)3-40
Flash Memory Operation
TMP19A43