tc9446fg TOSHIBA Semiconductor CORPORATION, tc9446fg Datasheet - Page 22

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tc9446fg

Manufacturer Part Number
tc9446fg
Description
Audio Digital Processor For Decode Of Dolby Digital Ac-3 , Mpeg2 Audio
Manufacturer
TOSHIBA Semiconductor CORPORATION
Datasheet
4. Read/Write of Command
5. Digital Audio Interface (DIR/DIT)
1)
2)
Figure 16 VCO Oscillation Circuit and Example of Composition of PLL
Setting of command register
Write and a read of command change with decode programs built in.
For details, please refer to program explanation data.
A setup of DIR/DIT
transmission (DIT) based on CEI “IEC958 standard” and the JEITA “CP-1201 standard” are built in.
DIR corresponds to the input of 96 kHz sampling (2 channels). Please refer to program explanation
data about the various contents of a setting of DIR/DIT.
VCO oscillation and PLL
filter simply. VCO oscillation circuit and the example of composition of PLL are shown in Figure 16.
The digital reception recovery (DIR) for the audio interfaces and the abnormal-conditions
Since VCO oscillation circuit is built in, PLL circuit can consist of connecting an external low path
(A) Crystal/XI clock
VCO circuit
generator
Selector
Timing
Modulation circuit
Phase detector
Demodulation
Frequency
detector
circuit
V
DD
/2
48
47
46
45
44
43
42
41
40
37
34
31
LOCK
CKO
V
CKI
AMPO
AMPI
PLON
V
PDO
FCONT
RX
TXO
22
SSA
DDA
DIR input
DIT output
Clock output
V
SSA
V
V
DDA
SSA
External clock input
(when CKI does not use, it
connect to V
L: CKI/XI clock
H: VCO clock
V
SS
SS
line.)
TC9446FG
2005-09-28

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