tc9446fg TOSHIBA Semiconductor CORPORATION, tc9446fg Datasheet - Page 24

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tc9446fg

Manufacturer Part Number
tc9446fg
Description
Audio Digital Processor For Decode Of Dolby Digital Ac-3 , Mpeg2 Audio
Manufacturer
TOSHIBA Semiconductor CORPORATION
Datasheet
6. DSP Part Clock Generating Circuit
5)
6)
generate the DLL clock of a crystal oscillation clock.
It is the circuit which generates a clock required in order to operate a decode program. DLL circuit can
DLL circuit and a crystal oscillation circuit block are shown in Figure 20.
FCONT Output
Non-inputted detection
time edge, VCO oscillation operates by free run. Since VCO oscillation frequency and CKO terminal
output are set to about 80 MHz, please change it to an external clock automatically by the internal
program at the time of less inputting, or choose XI input by setup of command register.
Miss lock detection
detected and the signal for escaping from a miss lock is outputted from FCONT terminal.
When existence of the edge of the input signal from RX terminal is detected and there is no fixed
By comparing the input signal and the oscillation frequency from RX terminal, a Miss lock is
Figure 20 Crystal Oscillation Circuit and DLL Circuit Block
(A) CKI/XI selector
Sampling Frequency (kHz)
Table 4 Non-Inputted Judgment Time of Input Signal
DLL oscillator
Figure 19 Miss Lock Detection Operation Timing
( * 3, * 4, * 6)
V
V
44.1
DD
SS
Higher than objective frequency
32
48
96
Internal DSP clock
Selector
24
Objective frequency
99
98
96
94
93
92
91
XI
XO
SCKI
SCKO
DLCKS
DLON
LPFO
Hiz
V
V
SS
SS
External clock input
(when the SCKI does not use,
it connect to V
Clock output
Time of Last Edge (ms)
V
SSX
Lower than objective frequency
approx. 1000
approx. 750
approx. 700
approx. 350
SS
line.)
TC9446FG
2005-09-28

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