lnbh25pqr STMicroelectronics, lnbh25pqr Datasheet - Page 16

• Manufacturer Part Number: lnbh25pqr
• Description: Lnb Supply And Control Ic With Step-up And I²c Interface
• Manufacturer: STMicroelectronics

I²C bus interface
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6.1
6.2
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6.4
6.5
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I²C bus interface
Data transmission from the main microprocessor to the LNBH25 and vice versa takes place
through the 2-wire I²C bus interface, consisting of the 2-line SDA and SCL (pull-up resistors
to positive supply voltage must be externally connected).
Data validity
As shown in
of the clock. The HIGH and LOW state of the data line can only change when the clock
signal on the SCL line is LOW.
Start and stop condition
As shown in
SCL is HIGH. The stop condition is a LOW to HIGH transition of the SDA line while SCL is
HIGH. A STOP condition must be sent before each START condition.
Byte format
Every byte transferred to the SDA line must contain 8 bits. Each byte must be followed by an
acknowledge bit. The MSB is transferred first.
Acknowledge
The master (microprocessor) puts a resistive HIGH level on the SDA line during the
acknowledge clock pulse (see
must pull down (LOW) the SDA line during the acknowledge clock pulse, so that the SDA
line is stable LOW during this clock pulse. The peripheral which has been addressed has to
generate acknowledge after the reception of each byte, otherwise the SDA line remains at
the HIGH level during the ninth clock pulse time. In this case the master transmitter can
generate the STOP information in order to abort the transfer. The LNBH25 won't generate
acknowledge if the V
Transmission without acknowledge
Avoiding to detect the acknowledges of the LNBH25, the microprocessor can use a simpler
transmission: it simply waits one clock without checking the slave acknowledging, and sends
the new data. This approach is of course less protected from misworking and decreases
noise immunity.
Figure 8
Figure 9
CC
, the data on the SDA line must be stable during the high semi-period
, a start condition is a HIGH to LOW transition of the SDA line while
supply is below the undervoltage lockout threshold (6.7 V typ.).
Doc ID 022433 Rev 3
Figure 10
). The peripheral (LNBH25) which acknowledges
LNBH25