lnbh25pqr STMicroelectronics, lnbh25pqr Datasheet - Page 20

• Manufacturer Part Number: lnbh25pqr
• Description: Lnb Supply And Control Ic With Step-up And I²c Interface
• Manufacturer: STMicroelectronics

I²C interface protocol
7.3
Table 7.
Table 8.
20/34
(MSB)
(MSB)
(LSB)
(LSB)
Bit 0
Bit 1
Bit 2
Bit 3
Bit 4
Bit 5
Bit 6
Bit 7
Bit 0
Bit 1
Bit 2
Bit 3
Bit 4
Bit 5
Bit 6
Bit 7
BIT
BIT
EXTM
Name
VSEL1
VSEL2
VSEL3
VSEL4
Data registers
The DATA 1..4 registers can be addressed both in write and read mode. In read mode they
return the last writing byte status received in the previous write transmission.
The following tables provide the Register Address values of Data 1..4 and a function
description of each bit.
DATA 1 (Read/Write register. Register address = 0X2)
N/A = Reserved bit.
All bits reset to “0” at power-on.
DATA 2 (Read/Write register. Register address = 0X3)
N/A = Reserved bit.
All bits reset to 0 at power-on.
Name
LPM
TEN
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
Value
Value
1
0
1
0
1
0
0
0
0
0
0
0/1
0/1
0/1
0/1
0
0
0
0
22 kHz tone enabled. Tone output controlled by DSQIN pin
22 kHz tone output disabled
Low power mode activated (used only with 22 kHz tone output disabled)
Low power mode deactivated (keep always LPM = 0 during 22 kHz tone
transmission)
DSQIN input pin is set to receive external 22 kHz TTL signal source
DSQIN input pin is set to receive external DiSEqC envelope TTL signal
Reserved. Keep to “0”
Reserved. Keep to "0"
Reserved. Keep to "0"
Reserved. Keep to "0"
Reserved. Keep to "0"
Output voltage selection bits. (Refer to
Reserved. Keep to "0"
Reserved. Keep to "0"
Reserved. Keep to "0"
Reserved. Keep to "0"
Doc ID 022433 Rev 3
Description
Description
Table 14
)
LNBH25