zl2103 Intersil Corporation, zl2103 Datasheet - Page 14

• Manufacturer Part Number: zl2103
• Description: 3a Digital-dc Synchronous Step-down Dc/dc Converter
• Manufacturer: Intersil Corporation

The resistor setting method can be used to set the output voltage
to levels not available in Table 2. To set V
Table 4 to select the resistor that corresponds to the desired
voltage.
The output voltage may also be set to any value between 0.6V
and 5.0V using the I
for details.
Start-up Procedure
The ZL2103 follows a specific internal start-up procedure after
power is applied to the VDD pins (VDDP and VDDS). Table 3
describes the start-up sequence.
TABLE 4. RESISTORS FOR SETTING OUTPUT VOLTAGE
R
12.1
13.3
14.7
16.2
17.8
19.6
21.5
23.7
26.1
28.7
31.6
34.8
38.3
42.2
46.4
51.1
56.2
61.9
68.1
82.5
90.9
(kΩ)
100
121
133
147
162
178
110
10
11
75
SET
2
C interface. See Application Note
14
OUT
using resistors, use
0.75
1.25
V
0.6
0.7
0.8
0.9
1.0
1.1
1.2
1.3
1.4
1.5
1.6
1.7
1.8
1.9
2.0
2.1
2.2
2.3
2.4
2.5
2.6
2.7
2.8
2.9
3.0
3.1
3.2
3.3
5.0
(V)
OUT
AN2033
ZL2103
If the device is to be synchronized to an external clock source, the
clock frequency must be stable prior to asserting the EN pin. The
device requires approximately 5ms to 10ms to check for specific
values stored in its internal memory. If the user has stored values
in memory, those values will be loaded. The device will then
check the status of all multi-mode pins and load the values
associated with the pin settings.
Once this process is completed, the device is ready to accept
commands via the I
to be enabled. Once enabled, the device requires approximately
2ms before its output voltage may be allowed to start its
ramp-up process. If a soft-start delay period less than 2ms has
been configured (using PMBus commands), the device will
default to a 2ms delay period. If a delay period greater than 2ms
is configured, the device will wait for the configured delay period
prior to starting to ramp its output.
After the delay period has expired, the output will begin to ramp
towards its target voltage according to the pre-configured
soft-start ramp time that has been set using the SS pin. It should
be noted that if the EN pin is tied to VDDP or VDDS, the device
will still require approximately 5ms to 10ms before the output
can begin its ramp-up as described in Table 3.
Soft-start Delay and Ramp Times
It may be necessary to set a delay from when an enable signal is
received until the output voltage starts to ramp to its target
value. In addition, the designer may wish to set the time required
for V
expired. These features may be used as part of an overall inrush
current management strategy or to control how fast a load IC is
turned on. The ZL2103 gives the system designer several options
for precisely and independently controlling both the delay and
ramp time periods.
The soft-start delay period begins when the EN pin is asserted
and ends when the delay time expires. The soft-start delay period
is set using the SS pin. Precise ramp delay timing mode reduces
the delay time variations and is available when the appropriate
bit in the MISC_CONFIG register had been set. Please refer to
Application Note
The soft-start ramp timer enables a precisely controlled ramp to
the nominal V
expired. The ramp-up is guaranteed monotonic and its slope may
be precisely set using the SS pin. Using the pin-strap method, the
soft-start delay and ramp times can be set to one of three
standard values according to Table 5.
If the desired soft-start delay and ramp times are not one of the
values listed in Table 5, the times can be set to a custom value by
connecting a resistor from the SS pin to SGND using the
SS PIN SETTING
OUT
OPEN
HIGH
to ramp to its target value after the delay period has
LOW
TABLE 5. SOFT-START DELAY AND RAMP SETTINGS
OUT
AN2033
value that begins once the delay period has
2
C/SMBus interface and the device is ready
for details.
RAMP TIME
DELAY AND
(ms)
10
2
5
UVLO
7.5V
May 3, 2011
FN6966.5