zl2103 Intersil Corporation, zl2103 Datasheet - Page 18

• Manufacturer Part Number: zl2103
• Description: 3a Digital-dc Synchronous Step-down Dc/dc Converter
• Manufacturer: Intersil Corporation

small output filter made possible by a higher switching frequency
and getting better power supply efficiency. Size can be decreased
by increasing the switching frequency at the expense of
efficiency. Cost can be minimized by using through-hole
inductors and capacitors; however these components are
physically large.
To start the design, select a frequency based on Table 11. This
frequency is a starting point and may be adjusted as the design
progresses.
INDUCTOR SELECTION
The output inductor selection process must include several
trade-offs. A high inductance value will result in a low ripple
current (I
a low output ripple voltage, but may also compromise output
transient load performance. Therefore, a balance must be struck
between output ripple and optimal load transient performance. A
good starting point is to select the output inductor ripple equal to
the expected load transient step magnitude (I
Now the output inductance can be calculated using Equation 3,
where V
The average inductor current is equal to the maximum output
current. The peak inductor current (I
Equation 4 where I
Select an inductor rated for the average DC current with a peak
current rating above the peak current computed in Equation 4.
In overcurrent or short-circuit conditions, the inductor may have
currents greater than 2X the normal maximum rated output
current. It is desirable to use an inductor that still provides some
inductance to protect the load and the internal MOSFETs from
damaging currents in this situation.
Once an inductor is selected, the DCR and core losses in the
inductor are calculated. Use the DCR specified in the inductor
manufacturer’s data sheet.
I
L
I
P
opp
Lpk
LDCR
OUT
FREQUENCY RANGE
200kHz to 400kHz
400kHz to 800kHz
=
=
800kHz to 1MHz
=
INM
=
I
I
opp
V
ostep
OUT
DCR
OUT
is the maximum input voltage:
TABLE 11. CIRCUIT DESIGN CONSIDERATIONS
), which will reduce output capacitance and produce
+
fsw
×
×
I
⎛
⎜ ⎜
⎝
OUT
opp
2
I
1
×
Lrms
−
I
is the maximum output current:
opp
V
V
2
OUT
INM
18
⎞
⎟ ⎟
⎠
EFFICIENCY
Moderate
Highest
Lower
Lpk
) is calculated using
ostep
):
CIRCUIT SIZE
Smallest
Smaller
Larger
(EQ. 2)
(EQ. 3)
(EQ. 5)
(EQ. 4)
ZL2103
I
where I
core loss of the selected inductor. Since this calculation is
specific to each inductor and manufacturer, refer to the chosen
inductor data sheet. Add the core loss and the DCR loss and
compare the total loss to the maximum power dissipation
recommendation in the inductor data sheet.
OUTPUT CAPACITOR SELECTION
Several trade-offs must also be considered when selecting an
output capacitor. Low ESR values are needed to have a small
output deviation during transient load steps (V
output voltage ripple (V
such as semi-stable (X5R and X7R) dielectric ceramic capacitors,
also have relatively low capacitance values. Many designs can
use a combination of high capacitance devices and low ESR
devices in parallel.
For high ripple currents, a low capacitance value can cause a
significant amount of output voltage ripple. Likewise, in high
transient load steps, a relatively large amount of capacitance is
needed to minimize the output voltage deviation while the
inductor current ramps up or down to the new steady state
output current value.
As a starting point, apportion one-half of the output ripple
voltage to the capacitor ESR and the other half to capacitance, as
shown in Equations 7 and 8:
Use these values to make an initial capacitor selection, using a
single capacitor or several capacitors in parallel.
After a capacitor has been selected, the resulting output voltage
ripple can be calculated using Equation 9:
Because each part of this equation was made to be less than or
equal to half of the allowed output ripple voltage, the V
be less than the desired maximum output ripple.
INPUT CAPACITOR
It is highly recommended that dedicated input capacitors be
used in any point-of-load design, even when the supply is
powered from a heavily filtered 5V or 12V “bulk” supply from an
off-line power supply. This is because of the high RMS ripple
current that is drawn by the buck converter topology. This ripple
(I
V
C
Lrms
I
ESR
I
CINrms
CINrms
Lrms
orip
OUT
is given by Equation 6:
=
=
=
) can be determined from Equation 10:
OUT
=
=
I
2
8
opp
is the maximum output current. Next, calculate the
V
×
I
I
×
OUT
OUT
orip
I
×
f
opp
sw
ESR
I
2
×
opp
×
+
V
( )
D
+
I
orip
orip
2
opp
12
×
8
). However, capacitors with low ESR,
×
1 ( D
2
f
−
sw
I
opp
×
)
C
OUT
osag
) and low
orip
May 3, 2011
(EQ. 10)
FN6966.5
should
(EQ. 6)
(EQ. 7)
(EQ. 8)
(EQ. 9)