zl2103 Intersil Corporation, zl2103 Datasheet - Page 25

• Manufacturer Part Number: zl2103
• Description: 3a Digital-dc Synchronous Step-down Dc/dc Converter
• Manufacturer: Intersil Corporation

Phase Spreading
When multiple point of load converters share a common DC
input supply, it is desirable to adjust the clock phase offset of
each device such that not all devices start to switch
simultaneously. Setting each converter to start its switching cycle
at a different point in time can dramatically reduce input
capacitance requirements and efficiency losses. Since the peak
current drawn from the input supply is effectively spread out over
a period of time, the peak current drawn at any given moment is
reduced and the power losses proportional to the I
reduced dramatically.
In order to enable phase spreading, all converters must be
synchronized to the same switching clock. The CFG pin is used to
set the configuration of the SYNC pin for each device as
described in “Switching Frequency and PLL” on page 16.
Selecting the phase offset for the device is accomplished by
selecting a device address according to the following equation:
Phase offset = device address x 45°
For example:
• A device address of 0x00 or 0x20 would configure no phase
• A device address of 0x01 or 0x21 would configure 45° of
• A device address of 0x02 or 0x22 would configure 90° of
The phase offset of each device may also be set to any value
between 0° and 360° in 22.5° increments via the I
interface. Refer to Application Note
Output Sequencing
A group of Zilker Labs devices may be configured to power up in
a predetermined sequence. This feature is especially useful when
powering advanced processors, FPGAs, and ASICs that require
one supply to reach its operating voltage prior to another supply
reaching its operating voltage in order to avoid latch-up from
occurring. Multi-device sequencing can be achieved by
configuring each device through the I
using Zilker Labs patented autonomous sequencing mode.
Autonomous sequencing mode configures sequencing by using
events transmitted between devices over the DDC bus.
The sequencing order is determined using each device’s SMBus
address. Using autonomous sequencing mode (configured using
the CFG pin), the devices must be assigned sequential SMBus
addresses with no missing addresses in the chain. This mode will
also constrain each device to have a phase offset according to its
SMBus address as described in section “Phase Spreading” on
page 25.
offset
phase offset
phase offset
25
AN2033
2
C/SMBus interface or by
for further details.
RMS
2
C/SMBus
2
are
ZL2103
The sequencing group will turn on in order starting with the
device with the lowest SMBus address and will continue through
to turn on each device in the address chain until all devices
connected have been turned on. When turning off, the device
with the highest SMBus address will turn off first followed in
reverse order by the other devices in the group.
Sequencing is configured by connecting a resistor from the CFG
pin to ground as described in Table 16. The CFG pin is also used
to set the configuration of the SYNC pin as well as to determine
the sequencing method and order. Please refer to section
“Switching Frequency and PLL” on page 16 for more details on
the operating parameters of the SYNC pin.
Multiple device sequencing may also be achieved by issuing
PMBus commands to assign the preceding device in the
sequencing chain as well as the device that will follow in the
sequencing chain. This method places fewer restrictions on the
SMBus address (no need of sequential address) and also allows
the user to assign any phase offset to any device irrespective of
its SMBus device address.
The Enable pins of all devices in a sequencing group must be tied
together and driven high to initiate a sequenced turn-on of the
group. Enable must be driven low to initiate a sequenced turnoff
of the group. Please refer to Application Note
on sequencing via the I
TABLE 16. CFG PIN CONFIGURATIONS FOR SEQUENCING AND
12.1kΩ
14.7kΩ
16.2kΩ
17.8kΩ
21.5kΩ
23.7kΩ
26.1kΩ
31.6kΩ
34.8kΩ
38.3kΩ
46.4kΩ
51.1kΩ
56.2kΩ
10kΩ
11kΩ
Open
R
High
Low
CFG
TRACKING
CONFIGURATION
Auto detect
Auto detect
Auto detect
Auto detect
Auto detect
Auto detect
SYNC PIN
Output
Output
Output
Output
Output
Output
Input
Input
Input
Input
Input
Input
2
C/SMBus interface.
Sequencing and Tracking are
disabled.
Sequencing and Tracking are
disabled.
Device is FIRST in nested
sequence. Tracking disabled.
Device is LAST in nested
sequence. Tracking disabled.
Device is MIDDLE in nested
sequence. Tracking disabled.
Sequence disabled. Tracking
enabled as defined in Table 13.
SEQUENCING CONFIGURATION
AN2033
for details
May 3, 2011
FN6966.5