tza1032 NXP Semiconductors, tza1032 Datasheet - Page 11

• Manufacturer Part Number: tza1032
• Description: Laser Driver And Controller Circuit
• Manufacturer: NXP Semiconductors

Philips Semiconductors
7
7.1
The TZA1032 has two possible I
input. This allows two TZA1032 ICs to be independently applied using the same I
applications), one with pin I2C_A0 HIGH and the other with pin I2C_A0 LOW. The TZA1032 operates as a slave only
I
Table 1 TZA1032 I
Each I
I
I
Table 2 I
7.2
The IRQ is built as an active LOW open-drain output pin so it can be linked to the system controller together with similar
signals in a wired-or approach. An IRQ register is present to select the conditions which can cause the IRQ line to be
active. Possible conditions for an interrupt can be overrun or under-run of threshold or delta laser current or several other
selectable conditions.
The status register allows extra signals to be monitored in non-interrupt mode (e.g. by polling). The IRQ and status
registers in combination with the IRQ line allow a very efficient way of controlling TZA1032.
In addition, the IRQ_enable register allows selectable masking of most of the IRQ conditions to the IRQ line.
2002 May 06
2
2
2
Write
Incremental write
RAM write
Read
Successive read
C-bus device.
C-bus interface are shown in Table 2. The special RAM Write mode allows fast block transfer of data via one single
C-bus register address.
Laser driver and controller circuit
FUNCTIONAL DESCRIPTION
I
2
2
C-BUS MODE
The I
Interrupt request
C-bus register has an 8-bit register address bus. The various modes in which an external controller can use the
2
C-bus communication modes supported by TZA1032
2
C-bus interface
1 = HIGH
0 = LOW
I2C_A0
2
C-bus addresses
start; TZA1032_write_address; acknowledge; register_address (n); acknowledge;
data_to_register_address (n); acknowledge; stop
start; TZA1032_write_address; acknowledge; register_address (n); acknowledge;
data_to_register_address (n); acknowledge; data_to_register_address (n + 1);
acknowledge; .... ; data_to_register_address (n + r); acknowledge; stop
start; TZA1032_write_address; acknowledge; register_address (= RAM x), acknowledge;
data_to_RAM x (0), acknowledge; data_to_RAM x (1), acknowledge; .... ;
data_to_RAM x (m); acknowledge; stop
start; TZA1032_write_address; acknowledge; register_address (n); acknowledge; stop
start; TZA1032_read_address; acknowledge; data_from_register_address (n);
acknowledge; stop
start; TZA1032_write_address; acknowledge; register_address (n); acknowledge; start;
TZA1032_read_address; acknowledge; data_from_register_address (n), acknowledge;
data_from_register_address (n); acknowledge; .... ; data_from_register_address (n);
acknowledge; stop
2
C-bus addresses that can be selected via pin I2C_A0, an active HIGH digital CMOS
1101 1100 (DCH)
1101 1110 (DEH)
I
2
C-BUS WRITE ADDRESS
11
I
2
C-BUS INFORMATION
1101 1101 (DDH)
1101 1111 (DFH)
2
C-bus (e.g. for double write
I
2
C-BUS READ ADDRESS
Preliminary specification
TZA1032