tza1032 NXP Semiconductors, tza1032 Datasheet - Page 12

• Manufacturer Part Number: tza1032
• Description: Laser Driver And Controller Circuit
• Manufacturer: NXP Semiconductors

Philips Semiconductors
7.3
TZA1032 has a soft reset register that can reset most of
the internal blocks, and is automatically synchronized with
the I
Most of the blocks in the TZA1032 are provided with a
power-down input. The IC features a special power-down
register which can be programmed via I
bit in the register causes a block to go into a low dissipation
standby mode. This offers the user the possibility to save
power when TZA1032 operates in a register mode (e.g.
during read).
7.4
The PLL is phase locked to the incoming RLC clock signal.
A single external clock signal is sufficient for a complete
task of TZA1032. The PLL unit provides all internal
clocking with the exception of the I
can run on its own SCL clock.
Table 3 Examples of PLL clock ratio programming
Note
1. The write strategy resolution is defined as the number of bits per RLC clock period.
7.5
A differential RLC receiver (DRX) with low voltage-swing is present to allow high data rates in combination with low
electromagnetic interference. The receiver features impedance matching with typical flex foils. Furthermore, single side
operation is optionally possible by connecting additional external resistors.
High-impedance input switching allows two or more TZA1032 ICs to operate in parallel. The high-impedance input switch
is controlled by a single I
high-impedance mode. A high-impedance input mode is also entered during Reset or power-down.
2002 May 06
CD
CD
CD
CD
CD
CD
CD
DVD
DVD
DVD
DVD
DVR-1
DVR-2
Laser driver and controller circuit
2
C-bus SCL input.
1
2
4
8
12
16
24
Soft reset and power-down
The Phase Locked Loop
The differential receiver
1
2
2.5
4
STANDARD
2
C-bus control register that can individually select DRX clock and/or data lines for
4.3218
8.6436
17.2872
34.5744
51.8616
69.1488
103.7232
26.16
52.32
65.4
104.64
65.625
93.75
2
C-bus interface that
RLC FREQUENCY
2
C-bus. An active
f
rlc
(MHz)
12
The PLL can be used in closed loop or as a stable
open-loop oscillator (in read mode for example) when no
input clock is present. For this purpose the PLL features a
self-learning oscillator mode for non-locked operation.
Furthermore, the PLL is designed for wide range
frequency locking (factor 2.5). The frequency
multiplication factor is programmable for flexible selection
of write strategy timing resolution for different standards
(CD 1 to 24 , DVD 1 , 2 , 4 and DVR).
For PLL characteristics see Table 3 for the possible PLL
frequencies and write strategy resolutions with respect to
the incoming RLC clock. The TZA1032 features are much
more flexible than shown in Table 3. The PLL frequency
and write strategy resolution can be programmed
according to the specific requirements of the user.
518.616
518.616
553.1904
553.1904
414.8928
553.1904
414.8928
523.2
523.2
392.4
418.56
525
562.5
PLL FREQUENCY
f
o
(MHz)
Preliminary specification
WRITE STRATEGY
RESOLUTION
TZA1032
20
10
8
8
8
8
8
8
4
6
4
8
6
(1)